pipe_ctx 2760 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data) pipe_ctx 2981 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c static bool all_displays_in_sync(const struct pipe_ctx pipe[], pipe_ctx 2984 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const struct pipe_ctx *active_pipes[MAX_PIPES]; pipe_ctx 3017 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const struct pipe_ctx pipe[], pipe_ctx 304 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c const struct pipe_ctx *pipe, pipe_ctx 444 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct pipe_ctx *pipe, pipe_ctx 512 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct pipe_ctx *primary_pipe, pipe_ctx 513 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct pipe_ctx *secondary_pipe) pipe_ctx 866 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1172 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1207 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; pipe_ctx 171 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 173 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (pipe_ctx->stream == NULL) pipe_ctx 177 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (pipe_ctx->top_pipe) pipe_ctx 180 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) pipe_ctx 181 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; pipe_ctx 186 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (dc_is_dp_signal(pipe_ctx->stream->signal) && pipe_ctx 187 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) pipe_ctx 188 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; pipe_ctx 132 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c const struct pipe_ctx *pipe_ctx = NULL; pipe_ctx 135 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c if (stream == context->res_ctx.pipe_ctx[k].stream) { pipe_ctx 136 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pipe_ctx = &context->res_ctx.pipe_ctx[k]; pipe_ctx 140 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ASSERT(pipe_ctx != NULL); pipe_ctx 147 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->signal = pipe_ctx->stream->signal; pipe_ctx 148 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; pipe_ctx 102 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 104 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (!pipe_ctx->plane_state) pipe_ctx 107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( pipe_ctx 108 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pipe_ctx->plane_res.dpp, pipe_ctx 110 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (!context->res_ctx.pipe_ctx[i].plane_state) pipe_ctx 113 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; pipe_ctx 114 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; pipe_ctx 284 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (!context->res_ctx.pipe_ctx[i].plane_state) pipe_ctx 287 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; pipe_ctx 288 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; pipe_ctx 301 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (!context->res_ctx.pipe_ctx[i].plane_state) pipe_ctx 304 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; pipe_ctx 305 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; pipe_ctx 289 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 317 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe = pipe_ctx 318 drivers/gpu/drm/amd/display/dc/core/dc.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 346 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe; pipe_ctx 351 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 396 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe; pipe_ctx 400 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 421 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipes = NULL; pipe_ctx 425 drivers/gpu/drm/amd/display/dc/core/dc.c if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == pipe_ctx 427 drivers/gpu/drm/amd/display/dc/core/dc.c pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 459 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipes; pipe_ctx 462 drivers/gpu/drm/amd/display/dc/core/dc.c if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { pipe_ctx 463 drivers/gpu/drm/amd/display/dc/core/dc.c pipes = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 476 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipes; pipe_ctx 479 drivers/gpu/drm/amd/display/dc/core/dc.c if (dc->current_state->res_ctx.pipe_ctx[i].stream pipe_ctx 482 drivers/gpu/drm/amd/display/dc/core/dc.c pipes = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 502 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipes_affected[MAX_PIPES]; pipe_ctx 509 drivers/gpu/drm/amd/display/dc/core/dc.c if (dc->current_state->res_ctx.pipe_ctx[j].stream pipe_ctx 512 drivers/gpu/drm/amd/display/dc/core/dc.c &dc->current_state->res_ctx.pipe_ctx[j]; pipe_ctx 756 drivers/gpu/drm/amd/display/dc/core/dc.c dc->current_state->res_ctx.pipe_ctx[i].stream; pipe_ctx 847 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL }; pipe_ctx 850 drivers/gpu/drm/amd/display/dc/core/dc.c if (!ctx->res_ctx.pipe_ctx[i].stream || pipe_ctx 851 drivers/gpu/drm/amd/display/dc/core/dc.c !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) pipe_ctx 853 drivers/gpu/drm/amd/display/dc/core/dc.c if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source) pipe_ctx 855 drivers/gpu/drm/amd/display/dc/core/dc.c multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i]; pipe_ctx 873 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; pipe_ctx 876 drivers/gpu/drm/amd/display/dc/core/dc.c if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe) pipe_ctx 879 drivers/gpu/drm/amd/display/dc/core/dc.c unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i]; pipe_ctx 884 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_set[MAX_PIPES]; pipe_ctx 910 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *temp; pipe_ctx 1034 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe; pipe_ctx 1038 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1040 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1059 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe; pipe_ctx 1094 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1125 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &context->res_ctx.pipe_ctx[k]; pipe_ctx 1188 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe; pipe_ctx 1191 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1219 drivers/gpu/drm/amd/display/dc/core/dc.c if (context->res_ctx.pipe_ctx[i].stream == NULL || pipe_ctx 1220 drivers/gpu/drm/amd/display/dc/core/dc.c context->res_ctx.pipe_ctx[i].plane_state == NULL) { pipe_ctx 1221 drivers/gpu/drm/amd/display/dc/core/dc.c context->res_ctx.pipe_ctx[i].pipe_idx = i; pipe_ctx 1222 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); pipe_ctx 1261 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i]; pipe_ctx 1264 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; pipe_ctx 1267 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; pipe_ctx 1270 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; pipe_ctx 1273 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; pipe_ctx 1362 drivers/gpu/drm/amd/display/dc/core/dc.c const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 1364 drivers/gpu/drm/amd/display/dc/core/dc.c if (plane_state == pipe_ctx->plane_state) { pipe_ctx 1903 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 1905 drivers/gpu/drm/amd/display/dc/core/dc.c if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { pipe_ctx 1909 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0); pipe_ctx 1913 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1); pipe_ctx 1919 drivers/gpu/drm/amd/display/dc/core/dc.c resource_build_info_frame(pipe_ctx); pipe_ctx 1920 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.update_info_frame(pipe_ctx); pipe_ctx 1931 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; pipe_ctx 1933 drivers/gpu/drm/amd/display/dc/core/dc.c resource_build_bit_depth_reduction_params(pipe_ctx->stream, pipe_ctx 1934 drivers/gpu/drm/amd/display/dc/core/dc.c &pipe_ctx->stream->bit_depth_params); pipe_ctx 1935 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, pipe_ctx 1950 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true); pipe_ctx 1951 drivers/gpu/drm/amd/display/dc/core/dc.c dp_update_dsc_config(pipe_ctx); pipe_ctx 1952 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false); pipe_ctx 1960 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.pipe_control_lock(dc, pipe_ctx, true); pipe_ctx 1963 drivers/gpu/drm/amd/display/dc/core/dc.c core_link_disable_stream(pipe_ctx); pipe_ctx 1965 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) pipe_ctx 1966 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); pipe_ctx 1973 drivers/gpu/drm/amd/display/dc/core/dc.c core_link_enable_stream(dc->current_state, pipe_ctx); pipe_ctx 1976 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.pipe_control_lock(dc, pipe_ctx, false); pipe_ctx 1979 drivers/gpu/drm/amd/display/dc/core/dc.c if (stream_update->abm_level && pipe_ctx->stream_res.abm) { pipe_ctx 1980 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->stream_res.tg->funcs->is_blanked) { pipe_ctx 1982 drivers/gpu/drm/amd/display/dc/core/dc.c if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) pipe_ctx 1983 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.abm->funcs->set_abm_level( pipe_ctx 1984 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.abm, stream->abm_level); pipe_ctx 1986 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.abm->funcs->set_abm_level( pipe_ctx 1987 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.abm, stream->abm_level); pipe_ctx 2002 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *top_pipe_to_program = NULL; pipe_ctx 2042 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 2043 drivers/gpu/drm/amd/display/dc/core/dc.c if (!pipe_ctx->plane_state) pipe_ctx 2045 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->plane_state != plane_state) pipe_ctx 2062 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 2064 drivers/gpu/drm/amd/display/dc/core/dc.c if (!pipe_ctx->top_pipe && pipe_ctx 2065 drivers/gpu/drm/amd/display/dc/core/dc.c !pipe_ctx->prev_odm_pipe && pipe_ctx 2066 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream && pipe_ctx 2067 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream == stream) { pipe_ctx 2070 drivers/gpu/drm/amd/display/dc/core/dc.c top_pipe_to_program = pipe_ctx; pipe_ctx 2072 drivers/gpu/drm/amd/display/dc/core/dc.c if (!pipe_ctx->plane_state) pipe_ctx 2080 drivers/gpu/drm/amd/display/dc/core/dc.c ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); pipe_ctx 2086 drivers/gpu/drm/amd/display/dc/core/dc.c dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); pipe_ctx 2090 drivers/gpu/drm/amd/display/dc/core/dc.c stream_get_status(context, pipe_ctx->stream); pipe_ctx 2093 drivers/gpu/drm/amd/display/dc/core/dc.c dc, pipe_ctx->stream, stream_status->plane_count, context); pipe_ctx 2111 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 2113 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->stream != stream) pipe_ctx 2116 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->plane_state != plane_state) pipe_ctx 2120 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.set_flip_control_gsl(pipe_ctx, pipe_ctx 2130 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 2132 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->stream != stream) pipe_ctx 2135 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->plane_state != plane_state) pipe_ctx 2143 drivers/gpu/drm/amd/display/dc/core/dc.c dc, pipe_ctx, plane_state->triplebuffer_flips); pipe_ctx 2147 drivers/gpu/drm/amd/display/dc/core/dc.c dc->hwss.update_plane_addr(dc, pipe_ctx); pipe_ctx 2156 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; pipe_ctx 2158 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->bottom_pipe || pipe_ctx 2159 drivers/gpu/drm/amd/display/dc/core/dc.c !pipe_ctx->stream || pipe_ctx 2160 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream != stream || pipe_ctx 2161 drivers/gpu/drm/amd/display/dc/core/dc.c !pipe_ctx->plane_state->update_flags.bits.addr_update) pipe_ctx 2164 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) pipe_ctx 2165 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); pipe_ctx 2204 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2205 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2220 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = pipe_ctx 2221 drivers/gpu/drm/amd/display/dc/core/dc.c &context->res_ctx.pipe_ctx[j]; pipe_ctx 2223 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->plane_state != surface) pipe_ctx 2226 drivers/gpu/drm/amd/display/dc/core/dc.c resource_build_scaling_params(pipe_ctx); pipe_ctx 2250 drivers/gpu/drm/amd/display/dc/core/dc.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2252 drivers/gpu/drm/amd/display/dc/core/dc.c if (pipe_ctx->plane_state && pipe_ctx->stream == stream) pipe_ctx 2253 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->plane_state->force_full_update = false; pipe_ctx 321 drivers/gpu/drm/amd/display/dc/core/dc_debug.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 325 drivers/gpu/drm/amd/display/dc/core/dc_debug.c if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) pipe_ctx 328 drivers/gpu/drm/amd/display/dc/core/dc_debug.c pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); pipe_ctx 333 drivers/gpu/drm/amd/display/dc/core/dc_debug.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 335 drivers/gpu/drm/amd/display/dc/core/dc_debug.c if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) pipe_ctx 339 drivers/gpu/drm/amd/display/dc/core/dc_debug.c pipe_ctx->stream_res.tg->inst, pipe_ctx 340 drivers/gpu/drm/amd/display/dc/core/dc_debug.c pipe_ctx->stream->timing.h_total, pipe_ctx 341 drivers/gpu/drm/amd/display/dc/core/dc_debug.c pipe_ctx->stream->timing.v_total, pipe_ctx 1429 drivers/gpu/drm/amd/display/dc/core/dc_link.c static void enable_stream_features(struct pipe_ctx *pipe_ctx) pipe_ctx 1431 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1452 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx) pipe_ctx 1454 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1477 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { pipe_ctx 1484 drivers/gpu/drm/amd/display/dc/core/dc_link.c dp_disable_link_phy(link, pipe_ctx->stream->signal); pipe_ctx 1492 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = pipe_ctx 1499 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->signal, pipe_ctx 1500 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->clock_source->id, pipe_ctx 1546 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx) pipe_ctx 1550 drivers/gpu/drm/amd/display/dc/core/dc_link.c status = enable_link_dp(state, pipe_ctx); pipe_ctx 1557 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx) pipe_ctx 1559 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_link *link = pipe_ctx->stream->link; pipe_ctx 1578 drivers/gpu/drm/amd/display/dc/core/dc_link.c return enable_link_dp(state, pipe_ctx); pipe_ctx 1581 drivers/gpu/drm/amd/display/dc/core/dc_link.c static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, pipe_ctx 1588 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->ctx->dc_bios->integrated_info; pipe_ctx 1678 drivers/gpu/drm/amd/display/dc/core/dc_link.c static bool i2c_write(struct pipe_ctx *pipe_ctx, pipe_ctx 1689 drivers/gpu/drm/amd/display/dc/core/dc_link.c cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; pipe_ctx 1697 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, pipe_ctx 1698 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link, &cmd)) pipe_ctx 1705 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx, pipe_ctx 1717 drivers/gpu/drm/amd/display/dc/core/dc_link.c DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); pipe_ctx 1729 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1752 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->ddc, pipe_ctx 1762 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1782 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1805 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->ddc, pipe_ctx 1815 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1834 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1846 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1858 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1871 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx, pipe_ctx 1878 drivers/gpu/drm/amd/display/dc/core/dc_link.c DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); pipe_ctx 1886 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1898 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1910 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1922 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1934 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1946 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1962 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1974 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1986 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 1998 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx, pipe_ctx 2004 drivers/gpu/drm/amd/display/dc/core/dc_link.c DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); pipe_ctx 2014 drivers/gpu/drm/amd/display/dc/core/dc_link.c i2c_success = i2c_write(pipe_ctx, slave_address, pipe_ctx 2027 drivers/gpu/drm/amd/display/dc/core/dc_link.c static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) pipe_ctx 2029 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2043 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { pipe_ctx 2044 drivers/gpu/drm/amd/display/dc/core/dc_link.c unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & pipe_ctx 2048 drivers/gpu/drm/amd/display/dc/core/dc_link.c eng_id = pipe_ctx->stream_res.stream_enc->id; pipe_ctx 2050 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { pipe_ctx 2051 drivers/gpu/drm/amd/display/dc/core/dc_link.c write_i2c_retimer_setting(pipe_ctx, pipe_ctx 2054 drivers/gpu/drm/amd/display/dc/core/dc_link.c write_i2c_default_retimer_setting(pipe_ctx, pipe_ctx 2059 drivers/gpu/drm/amd/display/dc/core/dc_link.c write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); pipe_ctx 2063 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx 2078 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->clock_source->id, pipe_ctx 2080 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->signal, pipe_ctx 2083 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx 2087 drivers/gpu/drm/amd/display/dc/core/dc_link.c static void enable_link_lvds(struct pipe_ctx *pipe_ctx) pipe_ctx 2089 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2100 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->clock_source->id, pipe_ctx 2108 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx) pipe_ctx 2111 drivers/gpu/drm/amd/display/dc/core/dc_link.c switch (pipe_ctx->stream->signal) { pipe_ctx 2113 drivers/gpu/drm/amd/display/dc/core/dc_link.c status = enable_link_dp(state, pipe_ctx); pipe_ctx 2116 drivers/gpu/drm/amd/display/dc/core/dc_link.c status = enable_link_edp(state, pipe_ctx); pipe_ctx 2119 drivers/gpu/drm/amd/display/dc/core/dc_link.c status = enable_link_dp_mst(state, pipe_ctx); pipe_ctx 2125 drivers/gpu/drm/amd/display/dc/core/dc_link.c enable_link_hdmi(pipe_ctx); pipe_ctx 2129 drivers/gpu/drm/amd/display/dc/core/dc_link.c enable_link_lvds(pipe_ctx); pipe_ctx 2140 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->link_status.link_active = true; pipe_ctx 2341 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) { pipe_ctx 2343 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx[i].stream->link pipe_ctx 2350 drivers/gpu/drm/amd/display/dc/core/dc_link.c res_ctx.pipe_ctx[i].stream_res.tg->inst + pipe_ctx 2356 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL) pipe_ctx 2432 drivers/gpu/drm/amd/display/dc/core/dc_link.c static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) pipe_ctx 2440 drivers/gpu/drm/amd/display/dc/core/dc_link.c bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth); pipe_ctx 2441 drivers/gpu/drm/amd/display/dc/core/dc_link.c kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); pipe_ctx 2514 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) pipe_ctx 2516 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2519 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; pipe_ctx 2539 drivers/gpu/drm/amd/display/dc/core/dc_link.c link, pipe_ctx->stream_res.stream_enc, &proposed_table); pipe_ctx 2545 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->pipe_idx); pipe_ctx 2583 drivers/gpu/drm/amd/display/dc/core/dc_link.c pbn = get_pbn_from_timing(pipe_ctx); pipe_ctx 2594 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) pipe_ctx 2596 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2599 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; pipe_ctx 2627 drivers/gpu/drm/amd/display/dc/core/dc_link.c link, pipe_ctx->stream_res.stream_enc, &proposed_table); pipe_ctx 2633 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->pipe_idx); pipe_ctx 2674 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe_ctx) pipe_ctx 2676 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc *core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 2677 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2679 drivers/gpu/drm/amd/display/dc/core/dc_link.c DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); pipe_ctx 2681 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) { pipe_ctx 2684 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->signal); pipe_ctx 2685 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( pipe_ctx 2686 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc, pipe_ctx 2687 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.tg->inst, pipe_ctx 2691 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 2692 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( pipe_ctx 2693 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc, pipe_ctx 2698 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) pipe_ctx 2699 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute( pipe_ctx 2700 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc, pipe_ctx 2703 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.audio != NULL); pipe_ctx 2705 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->link_state_valid = true; pipe_ctx 2707 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dvi_signal(pipe_ctx->stream->signal)) pipe_ctx 2708 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( pipe_ctx 2709 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc, pipe_ctx 2711 drivers/gpu/drm/amd/display/dc/core/dc_link.c (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? pipe_ctx 2714 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_lvds_signal(pipe_ctx->stream->signal)) pipe_ctx 2715 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute( pipe_ctx 2716 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.stream_enc, pipe_ctx 2721 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->apply_edp_fast_boot_optimization; pipe_ctx 2723 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->apply_edp_fast_boot_optimization = false; pipe_ctx 2725 drivers/gpu/drm/amd/display/dc/core/dc_link.c resource_build_info_frame(pipe_ctx); pipe_ctx 2726 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.update_info_frame(pipe_ctx); pipe_ctx 2729 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->apply_seamless_boot_optimization) { pipe_ctx 2730 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->dpms_off = false; pipe_ctx 2735 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && pipe_ctx 2737 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->dpms_off = false; pipe_ctx 2741 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->dpms_off) pipe_ctx 2744 drivers/gpu/drm/amd/display/dc/core/dc_link.c status = enable_link(state, pipe_ctx); pipe_ctx 2748 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->link_index, pipe_ctx 2757 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { pipe_ctx 2763 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.enable_audio_stream(pipe_ctx); pipe_ctx 2766 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) pipe_ctx 2767 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, pipe_ctx 2772 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->timing.flags.DSC) { pipe_ctx 2773 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dp_signal(pipe_ctx->stream->signal) || pipe_ctx 2774 drivers/gpu/drm/amd/display/dc/core/dc_link.c dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx 2775 drivers/gpu/drm/amd/display/dc/core/dc_link.c dp_set_dsc_enable(pipe_ctx, true); pipe_ctx 2778 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.enable_stream(pipe_ctx); pipe_ctx 2782 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->timing.flags.DSC) { pipe_ctx 2783 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dp_signal(pipe_ctx->stream->signal) || pipe_ctx 2784 drivers/gpu/drm/amd/display/dc/core/dc_link.c dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx 2785 drivers/gpu/drm/amd/display/dc/core/dc_link.c dp_set_dsc_pps_sdp(pipe_ctx, true); pipe_ctx 2789 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) pipe_ctx 2790 drivers/gpu/drm/amd/display/dc/core/dc_link.c allocate_mst_payload(pipe_ctx); pipe_ctx 2792 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.unblank_stream(pipe_ctx, pipe_ctx 2793 drivers/gpu/drm/amd/display/dc/core/dc_link.c &pipe_ctx->stream->link->cur_link_settings); pipe_ctx 2795 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 2796 drivers/gpu/drm/amd/display/dc/core/dc_link.c enable_stream_features(pipe_ctx); pipe_ctx 2800 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dp_signal(pipe_ctx->stream->signal) || pipe_ctx 2801 drivers/gpu/drm/amd/display/dc/core/dc_link.c dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx 2802 drivers/gpu/drm/amd/display/dc/core/dc_link.c dp_set_dsc_enable(pipe_ctx, true); pipe_ctx 2808 drivers/gpu/drm/amd/display/dc/core/dc_link.c void core_link_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 2810 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc *core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 2811 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2814 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.blank_stream(pipe_ctx); pipe_ctx 2816 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) pipe_ctx 2817 drivers/gpu/drm/amd/display/dc/core/dc_link.c deallocate_mst_payload(pipe_ctx); pipe_ctx 2819 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { pipe_ctx 2821 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; pipe_ctx 2832 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) pipe_ctx 2833 drivers/gpu/drm/amd/display/dc/core/dc_link.c write_i2c_retimer_setting(pipe_ctx, pipe_ctx 2836 drivers/gpu/drm/amd/display/dc/core/dc_link.c write_i2c_default_retimer_setting(pipe_ctx, pipe_ctx 2840 drivers/gpu/drm/amd/display/dc/core/dc_link.c write_i2c_redriver_setting(pipe_ctx, false); pipe_ctx 2843 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.disable_stream(pipe_ctx); pipe_ctx 2845 drivers/gpu/drm/amd/display/dc/core/dc_link.c disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); pipe_ctx 2847 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->timing.flags.DSC) { pipe_ctx 2848 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 2849 drivers/gpu/drm/amd/display/dc/core/dc_link.c dp_set_dsc_enable(pipe_ctx, false); pipe_ctx 2854 drivers/gpu/drm/amd/display/dc/core/dc_link.c void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx 2856 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct dc *core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 2858 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx 2861 drivers/gpu/drm/amd/display/dc/core/dc_link.c core_dc->hwss.set_avmute(pipe_ctx, enable); pipe_ctx 3004 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct pipe_ctx *pipe; pipe_ctx 3019 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 3050 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct pipe_ctx *pipe_ctx, pipe_ctx 3054 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_color_depth color_depth = pipe_ctx-> pipe_ctx 3057 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; pipe_ctx 3059 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c int width = pipe_ctx->stream->timing.h_addressable + pipe_ctx 3060 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.h_border_left + pipe_ctx 3061 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.h_border_right; pipe_ctx 3062 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c int height = pipe_ctx->stream->timing.v_addressable + pipe_ctx 3063 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.v_border_bottom + pipe_ctx 3064 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.v_border_top; pipe_ctx 3104 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->bit_depth_params = params; pipe_ctx 3106 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) pipe_ctx 3107 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, pipe_ctx 3111 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct pipe_ctx *odm_pipe; pipe_ctx 3114 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 3119 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 3143 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms); pipe_ctx 3144 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->bit_depth_params = params; pipe_ctx 3146 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) pipe_ctx 3147 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, pipe_ctx 3152 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct pipe_ctx *odm_pipe; pipe_ctx 3155 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 3159 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 3193 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; pipe_ctx 3194 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct pipe_ctx *pipe_ctx = &pipes[0]; pipe_ctx 3205 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx = &pipes[i]; pipe_ctx 3217 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c set_crtc_test_pattern(link, pipe_ctx, test_pattern); pipe_ctx 3224 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx, pipe_ctx 3251 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); pipe_ctx 3332 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c set_crtc_test_pattern(link, pipe_ctx, test_pattern); pipe_ctx 75 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct pipe_ctx *pipes = pipe_ctx 76 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c link->dc->current_state->res_ctx.pipe_ctx; pipe_ctx 272 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct pipe_ctx *pipes = pipe_ctx 273 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c &link->dc->current_state->res_ctx.pipe_ctx[0]; pipe_ctx 366 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx 368 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dc *core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 369 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 382 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx 384 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; pipe_ctx 385 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dc *core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 386 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 387 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct pipe_ctx *odm_pipe; pipe_ctx 390 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 408 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); pipe_ctx 409 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 422 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); pipe_ctx 424 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, pipe_ctx 433 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); pipe_ctx 435 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, pipe_ctx 441 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx 442 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.tg, pipe_ctx 447 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( pipe_ctx 448 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc, pipe_ctx 451 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx 452 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc, false, NULL); pipe_ctx 456 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); pipe_ctx 457 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 462 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx 464 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; pipe_ctx 467 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC) pipe_ctx 473 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (dp_set_dsc_on_rx(pipe_ctx, true)) { pipe_ctx 474 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dp_set_dsc_on_stream(pipe_ctx, true); pipe_ctx 478 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dp_set_dsc_on_rx(pipe_ctx, false); pipe_ctx 479 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dp_set_dsc_on_stream(pipe_ctx, false); pipe_ctx 486 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx 488 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; pipe_ctx 489 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dc *core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 490 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 492 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC || !dsc) pipe_ctx 509 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); pipe_ctx 510 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx 511 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc, pipe_ctx 518 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx 519 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.stream_enc, false, NULL); pipe_ctx 527 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx) pipe_ctx 529 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; pipe_ctx 531 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC) pipe_ctx 536 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dp_set_dsc_on_stream(pipe_ctx, true); pipe_ctx 537 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dp_set_dsc_pps_sdp(pipe_ctx, true); pipe_ctx 428 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct pipe_ctx *pipe_with_clk_src, pipe_ctx 429 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct pipe_ctx *pipe) pipe_ctx 460 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx) pipe_ctx 465 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) pipe_ctx 466 drivers/gpu/drm/amd/display/dc/core/dc_resource.c return res_ctx->pipe_ctx[i].clock_source; pipe_ctx 547 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static void calculate_viewport(struct pipe_ctx *pipe_ctx) pipe_ctx 549 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 550 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 551 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct scaler_data *data = &pipe_ctx->plane_res.scl_data; pipe_ctx 556 drivers/gpu/drm/amd/display/dc/core/dc_resource.c bool pri_split = pipe_ctx->bottom_pipe && pipe_ctx 557 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; pipe_ctx 558 drivers/gpu/drm/amd/display/dc/core/dc_resource.c bool sec_split = pipe_ctx->top_pipe && pipe_ctx 559 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; pipe_ctx 655 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static void calculate_recout(struct pipe_ctx *pipe_ctx) pipe_ctx 657 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 658 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 660 drivers/gpu/drm/amd/display/dc/core/dc_resource.c bool pri_split = pipe_ctx->bottom_pipe && pipe_ctx 661 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; pipe_ctx 662 drivers/gpu/drm/amd/display/dc/core/dc_resource.c bool sec_split = pipe_ctx->top_pipe && pipe_ctx 663 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; pipe_ctx 666 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; pipe_ctx 668 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x pipe_ctx 672 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * pipe_ctx 674 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > pipe_ctx 676 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width = pipe_ctx 678 drivers/gpu/drm/amd/display/dc/core/dc_resource.c - pipe_ctx->plane_res.scl_data.recout.x; pipe_ctx 680 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; pipe_ctx 682 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y pipe_ctx 686 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * pipe_ctx 688 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y > pipe_ctx 690 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height = pipe_ctx 692 drivers/gpu/drm/amd/display/dc/core/dc_resource.c - pipe_ctx->plane_res.scl_data.recout.y; pipe_ctx 696 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx 697 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height / 2; pipe_ctx 699 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height = pipe_ctx 700 drivers/gpu/drm/amd/display/dc/core/dc_resource.c (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2; pipe_ctx 702 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height /= 2; pipe_ctx 704 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx 705 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width / 2; pipe_ctx 707 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width = pipe_ctx 708 drivers/gpu/drm/amd/display/dc/core/dc_resource.c (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2; pipe_ctx 710 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width /= 2; pipe_ctx 713 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) pipe_ctx 715 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 716 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 724 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || pipe_ctx 725 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) pipe_ctx 728 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( pipe_ctx 731 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( pipe_ctx 736 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; pipe_ctx 738 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; pipe_ctx 740 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( pipe_ctx 741 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); pipe_ctx 742 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( pipe_ctx 743 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); pipe_ctx 745 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; pipe_ctx 746 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; pipe_ctx 748 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 pipe_ctx 749 drivers/gpu/drm/amd/display/dc/core/dc_resource.c || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { pipe_ctx 750 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; pipe_ctx 751 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; pipe_ctx 753 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( pipe_ctx 754 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz, 19); pipe_ctx 755 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( pipe_ctx 756 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert, 19); pipe_ctx 757 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( pipe_ctx 758 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); pipe_ctx 759 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( pipe_ctx 760 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); pipe_ctx 843 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx) pipe_ctx 845 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 846 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 847 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct scaler_data *data = &pipe_ctx->plane_res.scl_data; pipe_ctx 848 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct rect src = pipe_ctx->plane_state->src_rect; pipe_ctx 962 drivers/gpu/drm/amd/display/dc/core/dc_resource.c bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx 964 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 965 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; pipe_ctx 967 drivers/gpu/drm/amd/display/dc/core/dc_resource.c DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); pipe_ctx 972 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( pipe_ctx 973 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state->format); pipe_ctx 975 drivers/gpu/drm/amd/display/dc/core/dc_resource.c calculate_scaling_ratios(pipe_ctx); pipe_ctx 977 drivers/gpu/drm/amd/display/dc/core/dc_resource.c calculate_viewport(pipe_ctx); pipe_ctx 979 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16) pipe_ctx 982 drivers/gpu/drm/amd/display/dc/core/dc_resource.c calculate_recout(pipe_ctx); pipe_ctx 988 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; pipe_ctx 990 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; pipe_ctx 991 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; pipe_ctx 993 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; pipe_ctx 994 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; pipe_ctx 997 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.xfm != NULL) pipe_ctx 998 drivers/gpu/drm/amd/display/dc/core/dc_resource.c res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( pipe_ctx 999 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); pipe_ctx 1001 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.dpp != NULL) pipe_ctx 1002 drivers/gpu/drm/amd/display/dc/core/dc_resource.c res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( pipe_ctx 1003 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); pipe_ctx 1007 drivers/gpu/drm/amd/display/dc/core/dc_resource.c are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport, pipe_ctx 1008 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout)) { pipe_ctx 1009 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.taps.v_taps = 1; pipe_ctx 1010 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.taps.h_taps = 1; pipe_ctx 1015 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; pipe_ctx 1017 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.xfm != NULL) pipe_ctx 1018 drivers/gpu/drm/amd/display/dc/core/dc_resource.c res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( pipe_ctx 1019 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.xfm, pipe_ctx 1020 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &pipe_ctx->plane_res.scl_data, pipe_ctx 1023 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.dpp != NULL) pipe_ctx 1024 drivers/gpu/drm/amd/display/dc/core/dc_resource.c res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( pipe_ctx 1025 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp, pipe_ctx 1026 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &pipe_ctx->plane_res.scl_data, pipe_ctx 1032 drivers/gpu/drm/amd/display/dc/core/dc_resource.c calculate_inits_and_adj_vp(pipe_ctx); pipe_ctx 1039 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.height, pipe_ctx 1040 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.width, pipe_ctx 1041 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.x, pipe_ctx 1042 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.y, pipe_ctx 1059 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (context->res_ctx.pipe_ctx[i].plane_state != NULL && pipe_ctx 1060 drivers/gpu/drm/amd/display/dc/core/dc_resource.c context->res_ctx.pipe_ctx[i].stream != NULL) pipe_ctx 1061 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) pipe_ctx 1068 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *find_idle_secondary_pipe( pipe_ctx 1071 drivers/gpu/drm/amd/display/dc/core/dc_resource.c const struct pipe_ctx *primary_pipe) pipe_ctx 1074 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *secondary_pipe = NULL; pipe_ctx 1106 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { pipe_ctx 1107 drivers/gpu/drm/amd/display/dc/core/dc_resource.c secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; pipe_ctx 1118 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (res_ctx->pipe_ctx[i].stream == NULL) { pipe_ctx 1119 drivers/gpu/drm/amd/display/dc/core/dc_resource.c secondary_pipe = &res_ctx->pipe_ctx[i]; pipe_ctx 1128 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *resource_get_head_pipe_for_stream( pipe_ctx 1135 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (res_ctx->pipe_ctx[i].stream == stream pipe_ctx 1136 drivers/gpu/drm/amd/display/dc/core/dc_resource.c && !res_ctx->pipe_ctx[i].top_pipe pipe_ctx 1137 drivers/gpu/drm/amd/display/dc/core/dc_resource.c && !res_ctx->pipe_ctx[i].prev_odm_pipe) pipe_ctx 1138 drivers/gpu/drm/amd/display/dc/core/dc_resource.c return &res_ctx->pipe_ctx[i]; pipe_ctx 1143 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static struct pipe_ctx *resource_get_tail_pipe( pipe_ctx 1145 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *head_pipe) pipe_ctx 1147 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *tail_pipe; pipe_ctx 1163 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static struct pipe_ctx *acquire_free_pipe_for_head( pipe_ctx 1166 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *head_pipe) pipe_ctx 1176 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && pipe_ctx 1177 drivers/gpu/drm/amd/display/dc/core/dc_resource.c !res_ctx->pipe_ctx[i].plane_state) { pipe_ctx 1178 drivers/gpu/drm/amd/display/dc/core/dc_resource.c return &res_ctx->pipe_ctx[i]; pipe_ctx 1202 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; pipe_ctx 1238 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; pipe_ctx 1278 drivers/gpu/drm/amd/display/dc/core/dc_resource.c free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_ctx 1331 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1333 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_state == plane_state) { pipe_ctx 1334 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->top_pipe) pipe_ctx 1335 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; pipe_ctx 1341 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) pipe_ctx 1342 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; pipe_ctx 1348 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!pipe_ctx->top_pipe) pipe_ctx 1349 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state = NULL; pipe_ctx 1351 drivers/gpu/drm/amd/display/dc/core/dc_resource.c memset(pipe_ctx, 0, sizeof(*pipe_ctx)); pipe_ctx 1613 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!res_ctx->pipe_ctx[i].stream) { pipe_ctx 1614 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 1616 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.tg = pool->timing_generators[i]; pipe_ctx 1617 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.mi = pool->mis[i]; pipe_ctx 1618 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.hubp = pool->hubps[i]; pipe_ctx 1619 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx 1620 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx 1621 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp = pool->dpps[i]; pipe_ctx 1622 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[i]; pipe_ctx 1624 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; pipe_ctx 1625 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->pipe_idx = i; pipe_ctx 1628 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream = stream; pipe_ctx 1718 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); pipe_ctx 1719 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *odm_pipe; pipe_ctx 1751 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; pipe_ctx 1883 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!res_ctx->pipe_ctx[tg_inst].stream) { pipe_ctx 1884 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; pipe_ctx 1886 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; pipe_ctx 1887 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.mi = pool->mis[tg_inst]; pipe_ctx 1888 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; pipe_ctx 1889 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; pipe_ctx 1890 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; pipe_ctx 1891 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; pipe_ctx 1892 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[tg_inst]; pipe_ctx 1895 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; pipe_ctx 1896 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->pipe_idx = tg_inst; pipe_ctx 1898 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream = stream; pipe_ctx 1913 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = NULL; pipe_ctx 1952 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) pipe_ctx 1955 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_ctx 1957 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.stream_enc = pipe_ctx 1961 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!pipe_ctx->stream_res.stream_enc) pipe_ctx 1966 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.stream_enc, pipe_ctx 1971 drivers/gpu/drm/amd/display/dc/core/dc_resource.c dc_is_audio_capable_signal(pipe_ctx->stream->signal) && pipe_ctx 1973 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.audio = find_first_free_audio( pipe_ctx 1974 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id); pipe_ctx 1981 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->stream_res.audio) pipe_ctx 1983 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.audio, true); pipe_ctx 1987 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) pipe_ctx 1988 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.abm = pool->abm; pipe_ctx 1992 drivers/gpu/drm/amd/display/dc/core/dc_resource.c context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; pipe_ctx 1993 drivers/gpu/drm/amd/display/dc/core/dc_resource.c context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id; pipe_ctx 1995 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; pipe_ctx 2055 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; pipe_ctx 2057 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->stream != stream) pipe_ctx 2061 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state && pipe_ctx 2062 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { pipe_ctx 2063 drivers/gpu/drm/amd/display/dc/core/dc_resource.c result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state); pipe_ctx 2072 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (dc_is_dp_signal(pipe_ctx->stream->signal) && pipe_ctx 2078 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source); pipe_ctx 2080 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source = dc->res_pool->dp_clock_source; pipe_ctx 2084 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source); pipe_ctx 2119 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx) pipe_ctx 2121 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2134 drivers/gpu/drm/amd/display/dc/core/dc_resource.c unsigned int vic = pipe_ctx->stream->timing.vic; pipe_ctx 2139 drivers/gpu/drm/amd/display/dc/core/dc_resource.c color_space = pipe_ctx->stream->output_color_space; pipe_ctx 2300 drivers/gpu/drm/amd/display/dc/core/dc_resource.c switch (pipe_ctx->stream->timing.hdmi_vic) { pipe_ctx 2454 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; pipe_ctx 2457 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; pipe_ctx 2460 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; pipe_ctx 2463 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; pipe_ctx 2466 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; pipe_ctx 2495 drivers/gpu/drm/amd/display/dc/core/dc_resource.c void resource_build_info_frame(struct pipe_ctx *pipe_ctx) pipe_ctx 2498 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; pipe_ctx 2508 drivers/gpu/drm/amd/display/dc/core/dc_resource.c signal = pipe_ctx->stream->signal; pipe_ctx 2512 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_avi_info_frame(&info->avi, pipe_ctx); pipe_ctx 2514 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_vendor_info_packet(&info->vendor, pipe_ctx->stream); pipe_ctx 2516 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_spd_info_packet(&info->spd, pipe_ctx->stream); pipe_ctx 2518 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); pipe_ctx 2521 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_vsc_info_packet(&info->vsc, pipe_ctx->stream); pipe_ctx 2523 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_spd_info_packet(&info->spd, pipe_ctx->stream); pipe_ctx 2525 drivers/gpu/drm/amd/display/dc/core/dc_resource.c set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); pipe_ctx 2538 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( pipe_ctx 2541 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!pipe_ctx) pipe_ctx 2544 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (dc_is_dp_signal(pipe_ctx->stream->signal) pipe_ctx 2545 drivers/gpu/drm/amd/display/dc/core/dc_resource.c || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) pipe_ctx 2546 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source = pool->dp_clock_source; pipe_ctx 2548 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source = NULL; pipe_ctx 2551 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( pipe_ctx 2553 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx); pipe_ctx 2555 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->clock_source == NULL) pipe_ctx 2556 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source = pipe_ctx 2562 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->clock_source == NULL) pipe_ctx 2567 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->clock_source); pipe_ctx 2578 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx_old, pipe_ctx 2579 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx) pipe_ctx 2584 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) pipe_ctx 2587 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) pipe_ctx 2590 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) pipe_ctx 2593 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx_old->clock_source != pipe_ctx->clock_source pipe_ctx 2594 drivers/gpu/drm/amd/display/dc/core/dc_resource.c && pipe_ctx_old->stream != pipe_ctx->stream) pipe_ctx 2597 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) pipe_ctx 2600 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) pipe_ctx 2603 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream)) pipe_ctx 2606 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) pipe_ctx 2609 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream)) pipe_ctx 238 drivers/gpu/drm/amd/display/dc/core/dc_stream.c static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc) pipe_ctx 243 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 249 drivers/gpu/drm/amd/display/dc/core/dc_stream.c vupdate_line = get_vupdate_offset_from_vsync(pipe_ctx); pipe_ctx 277 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe_to_program = NULL; pipe_ctx 298 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 300 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (pipe_ctx->stream != stream) pipe_ctx 304 drivers/gpu/drm/amd/display/dc/core/dc_stream.c pipe_to_program = pipe_ctx; pipe_ctx 306 drivers/gpu/drm/amd/display/dc/core/dc_stream.c delay_cursor_until_vupdate(pipe_ctx, core_dc); pipe_ctx 310 drivers/gpu/drm/amd/display/dc/core/dc_stream.c core_dc->hwss.set_cursor_attribute(pipe_ctx); pipe_ctx 312 drivers/gpu/drm/amd/display/dc/core/dc_stream.c core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx); pipe_ctx 328 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe_to_program = NULL; pipe_ctx 345 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 347 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (pipe_ctx->stream != stream || pipe_ctx 348 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || pipe_ctx 349 drivers/gpu/drm/amd/display/dc/core/dc_stream.c !pipe_ctx->plane_state || pipe_ctx 350 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || pipe_ctx 351 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) pipe_ctx 355 drivers/gpu/drm/amd/display/dc/core/dc_stream.c pipe_to_program = pipe_ctx; pipe_ctx 357 drivers/gpu/drm/amd/display/dc/core/dc_stream.c delay_cursor_until_vupdate(pipe_ctx, core_dc); pipe_ctx 361 drivers/gpu/drm/amd/display/dc/core/dc_stream.c core_dc->hwss.set_cursor_position(pipe_ctx); pipe_ctx 493 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; pipe_ctx 495 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (res_ctx->pipe_ctx[i].stream != stream) pipe_ctx 521 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 523 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (pipe_ctx->stream != stream) pipe_ctx 527 drivers/gpu/drm/amd/display/dc/core/dc_stream.c dc->hwss.send_immediate_sdp_message(pipe_ctx, pipe_ctx 552 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; pipe_ctx 554 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (res_ctx->pipe_ctx[i].stream != stream) pipe_ctx 574 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe = NULL; pipe_ctx 581 drivers/gpu/drm/amd/display/dc/core/dc_stream.c pipe = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 597 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct pipe_ctx *pipe_ctx = NULL; pipe_ctx 610 drivers/gpu/drm/amd/display/dc/core/dc_stream.c pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 611 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (pipe_ctx->stream == stream) pipe_ctx 618 drivers/gpu/drm/amd/display/dc/core/dc_stream.c hubp = pipe_ctx->plane_res.hubp; pipe_ctx 622 drivers/gpu/drm/amd/display/dc/core/dc_stream.c pipe_ctx->stream->dmdata_address = attr->address; pipe_ctx 624 drivers/gpu/drm/amd/display/dc/core/dc_stream.c dc->hwss.program_dmdata_engine(pipe_ctx); pipe_ctx 627 drivers/gpu/drm/amd/display/dc/core/dc_stream.c pipe_ctx->stream->dmdata_address.quad_part != 0) { pipe_ctx 162 drivers/gpu/drm/amd/display/dc/core/dc_surface.c struct pipe_ctx *pipe_ctx = pipe_ctx 163 drivers/gpu/drm/amd/display/dc/core/dc_surface.c &core_dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 165 drivers/gpu/drm/amd/display/dc/core/dc_surface.c if (pipe_ctx->plane_state != plane_state) pipe_ctx 168 drivers/gpu/drm/amd/display/dc/core/dc_surface.c pipe_ctx->plane_state->status.is_flip_pending = false; pipe_ctx 174 drivers/gpu/drm/amd/display/dc/core/dc_surface.c struct pipe_ctx *pipe_ctx = pipe_ctx 175 drivers/gpu/drm/amd/display/dc/core/dc_surface.c &core_dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 177 drivers/gpu/drm/amd/display/dc/core/dc_surface.c if (pipe_ctx->plane_state != plane_state) pipe_ctx 180 drivers/gpu/drm/amd/display/dc/core/dc_surface.c core_dc->hwss.update_pending_status(pipe_ctx); pipe_ctx 190 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 192 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (pipe_ctx->stream == NULL) pipe_ctx 196 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (pipe_ctx->top_pipe) pipe_ctx 199 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) pipe_ctx 200 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; pipe_ctx 205 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (dc_is_dp_signal(pipe_ctx->stream->signal) && pipe_ctx 206 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) pipe_ctx 207 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; pipe_ctx 504 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c const struct pipe_ctx *pipe_ctx = NULL; pipe_ctx 507 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (stream == context->res_ctx.pipe_ctx[k].stream) { pipe_ctx 508 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pipe_ctx = &context->res_ctx.pipe_ctx[k]; pipe_ctx 512 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c ASSERT(pipe_ctx != NULL); pipe_ctx 519 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->signal = pipe_ctx->stream->signal; pipe_ctx 520 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; pipe_ctx 48 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c struct pipe_ctx *pipe, pipe_ctx 826 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h struct pipe_ctx *pipe, pipe_ctx 753 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); pipe_ctx 755 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!pipe_ctx) pipe_ctx 758 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce110_resource_build_pipe_hw_param(pipe_ctx); pipe_ctx 760 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c resource_build_info_frame(pipe_ctx); pipe_ctx 774 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (context->res_ctx.pipe_ctx[i].stream) pipe_ctx 271 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 274 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; pipe_ctx 599 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 602 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct transform *xfm = pipe_ctx->plane_res.xfm; pipe_ctx 624 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) pipe_ctx 629 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ASSERT(pipe_ctx->stream); pipe_ctx 631 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.stream_enc == NULL) pipe_ctx 634 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); pipe_ctx 635 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); pipe_ctx 641 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( pipe_ctx 642 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, pipe_ctx 643 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream_res.encoder_info_frame); pipe_ctx 645 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( pipe_ctx 646 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, pipe_ctx 647 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream_res.encoder_info_frame); pipe_ctx 650 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_enable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 653 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->link->cur_link_settings.lane_count; pipe_ctx 655 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; pipe_ctx 656 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_link *link = pipe_ctx->stream->link; pipe_ctx 661 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 668 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->id, true); pipe_ctx 670 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c link->dc->hwss.update_info_frame(pipe_ctx); pipe_ctx 687 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio != NULL) { pipe_ctx 688 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 689 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); pipe_ctx 943 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 951 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->stream) pipe_ctx 954 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c core_dc = pipe_ctx->stream->ctx->dc; pipe_ctx 957 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) pipe_ctx 963 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio) { pipe_ctx 966 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) pipe_ctx 970 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); pipe_ctx 977 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( pipe_ctx 978 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, false); pipe_ctx 979 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio) pipe_ctx 980 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->enabled = true; pipe_ctx 984 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 990 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx || !pipe_ctx->stream) pipe_ctx 993 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc = pipe_ctx->stream->ctx->dc; pipe_ctx 996 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) pipe_ctx 999 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( pipe_ctx 1000 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, true); pipe_ctx 1001 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio) { pipe_ctx 1002 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->enabled = false; pipe_ctx 1007 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 1008 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( pipe_ctx 1009 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc); pipe_ctx 1011 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( pipe_ctx 1012 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc); pipe_ctx 1026 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 1028 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1030 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc *dc = pipe_ctx->stream->ctx->dc; pipe_ctx 1032 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { pipe_ctx 1033 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( pipe_ctx 1034 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc); pipe_ctx 1035 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( pipe_ctx 1036 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc); pipe_ctx 1039 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 1040 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( pipe_ctx 1041 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc); pipe_ctx 1043 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.disable_audio_stream(pipe_ctx); pipe_ctx 1047 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->id, pipe_ctx 1052 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, pipe_ctx 1056 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1060 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.timing = pipe_ctx->stream->timing; pipe_ctx 1063 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 1064 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); pipe_ctx 1071 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_blank_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 1073 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1081 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 1082 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); pipe_ctx 1086 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx 1088 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) pipe_ctx 1089 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); pipe_ctx 1114 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c const struct pipe_ctx *pipe_ctx, pipe_ctx 1117 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1118 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; pipe_ctx 1120 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->signal = pipe_ctx->stream->signal; pipe_ctx 1154 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; pipe_ctx 1157 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; pipe_ctx 1160 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx 1163 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { pipe_ctx 1167 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; pipe_ctx 1172 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || pipe_ctx 1173 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { pipe_ctx 1180 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pll_settings.feedback_divider; pipe_ctx 1184 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->inst + 1); pipe_ctx 1190 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pll_settings.ss_percentage; pipe_ctx 1193 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, pipe_ctx 1196 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; pipe_ctx 1198 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c switch (pipe_ctx->plane_res.scl_data.format) { pipe_ctx 1229 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c const struct pipe_ctx *pipe_ctx) pipe_ctx 1235 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) pipe_ctx 1240 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c get_surface_visual_confirm_color(pipe_ctx, &color); pipe_ctx 1243 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->output_color_space, pipe_ctx 1246 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( pipe_ctx 1247 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm, pipe_ctx 1248 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.depth, pipe_ctx 1249 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream->bit_depth_params); pipe_ctx 1251 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { pipe_ctx 1257 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) pipe_ctx 1260 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( pipe_ctx 1261 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 1265 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, pipe_ctx 1266 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->plane_res.scl_data); pipe_ctx 1270 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 1274 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1275 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx 1276 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[pipe_ctx->pipe_idx]; pipe_ctx 1284 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_blank_color( pipe_ctx 1285 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 1292 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); pipe_ctx 1294 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx 1295 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->clock_source, pipe_ctx 1296 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream_res.pix_clk_params, pipe_ctx 1297 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->pll_settings)) { pipe_ctx 1302 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->program_timing( pipe_ctx 1303 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 1309 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->signal, pipe_ctx 1314 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( pipe_ctx 1315 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg)) { pipe_ctx 1325 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 1329 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1333 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; pipe_ctx 1337 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.disable_stream_gating(dc, pipe_ctx); pipe_ctx 1340 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio != NULL) { pipe_ctx 1343 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c build_audio_output(context, pipe_ctx, &audio_output); pipe_ctx 1345 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 1346 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( pipe_ctx 1347 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, pipe_ctx 1348 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->inst, pipe_ctx 1349 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream->audio_info); pipe_ctx 1351 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( pipe_ctx 1352 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, pipe_ctx 1353 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->inst, pipe_ctx 1354 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream->audio_info, pipe_ctx 1357 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->funcs->az_configure( pipe_ctx 1358 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio, pipe_ctx 1359 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->signal, pipe_ctx 1361 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->stream->audio_info); pipe_ctx 1366 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->stream->apply_seamless_boot_optimization) pipe_ctx 1367 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.enable_stream_timing(pipe_ctx, context, dc); pipe_ctx 1370 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.setup_vupdate_interrupt(pipe_ctx); pipe_ctx 1374 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.tg->funcs->set_drr) pipe_ctx 1375 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_drr( pipe_ctx 1376 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg, ¶ms); pipe_ctx 1381 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) pipe_ctx 1382 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx 1383 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg, event_triggers); pipe_ctx 1385 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx 1386 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( pipe_ctx 1387 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.stream_enc, pipe_ctx 1388 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->inst); pipe_ctx 1390 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( pipe_ctx 1391 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp, pipe_ctx 1396 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx 1397 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp, pipe_ctx 1417 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c core_link_enable_stream(context, pipe_ctx); pipe_ctx 1419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; pipe_ctx 1421 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->link->psr_enabled = false; pipe_ctx 1514 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; pipe_ctx 1516 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]); pipe_ctx 1654 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1657 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == NULL) pipe_ctx 1661 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->bw_vbios->blackout_duration, pipe_ctx->stream); pipe_ctx 1662 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( pipe_ctx 1663 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi, pipe_ctx 1671 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( pipe_ctx 1672 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi, pipe_ctx 1695 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) pipe_ctx 1698 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( pipe_ctx 1699 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c res_ctx->pipe_ctx[i].plane_res.mi, pipe_ctx 1707 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( pipe_ctx 1708 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c res_ctx->pipe_ctx[i].plane_res.mi, pipe_ctx 1721 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void set_drr(struct pipe_ctx **pipe_ctx, pipe_ctx 1738 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs->set_drr( pipe_ctx 1739 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[i]->stream_res.tg, ¶ms); pipe_ctx 1742 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( pipe_ctx 1743 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[i]->stream_res.tg, pipe_ctx 1748 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void get_position(struct pipe_ctx **pipe_ctx, pipe_ctx 1757 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); pipe_ctx 1760 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void set_static_screen_control(struct pipe_ctx **pipe_ctx, pipe_ctx 1776 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc *dc = pipe_ctx[0]->stream->ctx->dc; pipe_ctx 1783 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs-> pipe_ctx 1784 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); pipe_ctx 1795 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = NULL; pipe_ctx 1811 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (res_ctx->pipe_ctx[i].stream) { pipe_ctx 1813 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx 1815 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx) pipe_ctx 1819 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->pipe_idx != underlay_idx) { pipe_ctx 1829 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->stream->link) pipe_ctx 1833 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) pipe_ctx 1837 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->link->psr_enabled) pipe_ctx 1841 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->plane_state) pipe_ctx 1845 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) pipe_ctx 1864 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_ctx 1866 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.source_view_width = pipe_ctx->stream->timing.h_addressable; pipe_ctx 1867 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.source_view_height = pipe_ctx->stream->timing.v_addressable; pipe_ctx 1868 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.inst = pipe_ctx->stream_res.tg->inst; pipe_ctx 1887 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx_old = pipe_ctx 1888 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1889 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1900 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->stream || pipe_ctx 1901 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { pipe_ctx 1907 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { pipe_ctx 1974 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1976 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == NULL) pipe_ctx 1979 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->top_pipe) pipe_ctx 1982 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) pipe_ctx 1985 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio != NULL) { pipe_ctx 1988 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c build_audio_output(context, pipe_ctx, &audio_output); pipe_ctx 1990 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx 1991 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio, pipe_ctx 1992 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->signal, pipe_ctx 2002 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2004 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == NULL) pipe_ctx 2007 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->top_pipe) pipe_ctx 2010 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 2013 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream_res.audio != NULL) { pipe_ctx 2016 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c build_audio_output(context, pipe_ctx, &audio_output); pipe_ctx 2018 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx 2019 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.audio, pipe_ctx 2020 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->signal, pipe_ctx 2050 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx_old = pipe_ctx 2051 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2052 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2054 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) pipe_ctx 2057 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == pipe_ctx_old->stream) { pipe_ctx 2058 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) pipe_ctx 2060 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->clock_source, i); pipe_ctx 2075 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx_old = pipe_ctx 2076 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2077 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2079 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == NULL) pipe_ctx 2082 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream == pipe_ctx_old->stream && pipe_ctx 2083 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->link->link_state_valid) { pipe_ctx 2087 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) pipe_ctx 2090 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) pipe_ctx 2094 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx, pipe_ctx 2113 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void set_default_colors(struct pipe_ctx *pipe_ctx) pipe_ctx 2118 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.in_color_space = pipe_ctx->plane_state->color_space; pipe_ctx 2119 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.out_color_space = pipe_ctx->stream->output_color_space; pipe_ctx 2121 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; pipe_ctx 2125 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.display_color_depth; pipe_ctx 2128 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; pipe_ctx 2130 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( pipe_ctx 2131 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm, &default_adjust); pipe_ctx 2155 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx) pipe_ctx 2160 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->bottom_pipe) { pipe_ctx 2163 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); pipe_ctx 2165 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->bottom_pipe->plane_state->visible) { pipe_ctx 2166 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_state->visible) pipe_ctx 2171 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c } else if (!pipe_ctx->plane_state->visible) pipe_ctx 2174 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c } else if (!pipe_ctx->plane_state->visible) pipe_ctx 2177 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); pipe_ctx 2178 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); pipe_ctx 2182 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void program_gamut_remap(struct pipe_ctx *pipe_ctx) pipe_ctx 2190 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { pipe_ctx 2195 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->gamut_remap_matrix.matrix[i]; pipe_ctx 2198 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); pipe_ctx 2201 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx) pipe_ctx 2203 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 2208 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx 2209 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi, pipe_ctx 2216 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) pipe_ctx 2218 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 2224 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( pipe_ctx 2225 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi); pipe_ctx 2228 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; pipe_ctx 2230 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; pipe_ctx 2231 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && pipe_ctx 2232 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { pipe_ctx 2234 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); pipe_ctx 2286 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *grouped_pipes[]) pipe_ctx 2331 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *grouped_pipes[]) pipe_ctx 2464 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 2466 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct mem_input *mi = pipe_ctx->plane_res.mi; pipe_ctx 2467 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *old_pipe = NULL; pipe_ctx 2468 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 2476 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; pipe_ctx 2483 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c set_default_colors(pipe_ctx); pipe_ctx 2484 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->csc_color_matrix.enable_adjustment pipe_ctx 2487 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->output_color_space; pipe_ctx 2491 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx 2493 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment pipe_ctx 2494 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (pipe_ctx->plane_res.xfm, &tbl_entry); pipe_ctx 2497 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { pipe_ctx 2502 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->gamut_remap_matrix.matrix[i]; pipe_ctx 2505 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); pipe_ctx 2507 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; pipe_ctx 2509 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c program_scaler(dc, pipe_ctx); pipe_ctx 2520 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); pipe_ctx 2524 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi, pipe_ctx 2530 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_state->update_flags.bits.full_update || pipe_ctx 2531 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || pipe_ctx 2532 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->update_flags.bits.gamma_change) pipe_ctx 2533 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); pipe_ctx 2535 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_state->update_flags.bits.full_update) pipe_ctx 2536 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); pipe_ctx 2544 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pipe_idx, pipe_ctx 2545 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (void *) pipe_ctx->plane_state, pipe_ctx 2546 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->address.grph.addr.high_part, pipe_ctx 2547 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->address.grph.addr.low_part, pipe_ctx 2548 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->src_rect.x, pipe_ctx 2549 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->src_rect.y, pipe_ctx 2550 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->src_rect.width, pipe_ctx 2551 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->src_rect.height, pipe_ctx 2552 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->dst_rect.x, pipe_ctx 2553 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->dst_rect.y, pipe_ctx 2554 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->dst_rect.width, pipe_ctx 2555 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->dst_rect.height, pipe_ctx 2556 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->clip_rect.x, pipe_ctx 2557 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->clip_rect.y, pipe_ctx 2558 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->clip_rect.width, pipe_ctx 2559 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_state->clip_rect.height); pipe_ctx 2565 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pipe_idx, pipe_ctx 2566 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.width, pipe_ctx 2567 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.height, pipe_ctx 2568 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.x, pipe_ctx 2569 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.y, pipe_ctx 2570 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.width, pipe_ctx 2571 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.height, pipe_ctx 2572 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.x, pipe_ctx 2573 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.y); pipe_ctx 2591 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2592 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2594 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (stream == pipe_ctx->stream) { pipe_ctx 2595 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (!pipe_ctx->top_pipe && pipe_ctx 2596 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) pipe_ctx 2597 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.pipe_control_lock(dc, pipe_ctx, true); pipe_ctx 2602 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2604 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream != stream) pipe_ctx 2608 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->allocate_mem_input( pipe_ctx 2609 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi, pipe_ctx 2610 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.h_total, pipe_ctx 2611 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.v_total, pipe_ctx 2612 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.pix_clk_100hz / 10, pipe_ctx 2615 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dce110_program_front_end_for_pipe(dc, pipe_ctx); pipe_ctx 2617 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.update_plane_addr(dc, pipe_ctx); pipe_ctx 2619 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c program_surface_visibility(dc, pipe_ctx); pipe_ctx 2624 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2625 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2627 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if ((stream == pipe_ctx->stream) && pipe_ctx 2628 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (!pipe_ctx->top_pipe) && pipe_ctx 2629 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) pipe_ctx 2630 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->hwss.pipe_control_lock(dc, pipe_ctx, false); pipe_ctx 2637 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 2639 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c int fe_idx = pipe_ctx->plane_res.mi ? pipe_ctx 2640 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; pipe_ctx 2643 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) pipe_ctx 2656 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx) pipe_ctx 2662 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 2670 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { pipe_ctx 2671 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c enum dc_color_space color_space = pipe_ctx->stream->output_color_space; pipe_ctx 2674 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx 2678 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( pipe_ctx 2679 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm, &tbl_entry); pipe_ctx 2683 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) pipe_ctx 2685 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; pipe_ctx 2686 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; pipe_ctx 2687 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct mem_input *mi = pipe_ctx->plane_res.mi; pipe_ctx 2689 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, pipe_ctx 2690 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, pipe_ctx 2691 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .viewport = pipe_ctx->plane_res.scl_data.viewport, pipe_ctx 2692 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, pipe_ctx 2693 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, pipe_ctx 2694 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .rotation = pipe_ctx->plane_state->rotation, pipe_ctx 2695 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .mirror = pipe_ctx->plane_state->horizontal_mirror pipe_ctx 2698 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_state->address.type pipe_ctx 2702 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) pipe_ctx 2711 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) pipe_ctx 2713 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; pipe_ctx 2715 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_res.ipp && pipe_ctx 2716 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) pipe_ctx 2717 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( pipe_ctx 2718 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.ipp, attributes); pipe_ctx 2720 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_res.mi && pipe_ctx 2721 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) pipe_ctx 2722 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( pipe_ctx 2723 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi, attributes); pipe_ctx 2725 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_res.xfm && pipe_ctx 2726 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) pipe_ctx 2727 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( pipe_ctx 2728 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.xfm, attributes); pipe_ctx 43 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_enable_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 45 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_disable_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 47 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, pipe_ctx 50 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_blank_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 52 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 53 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 55 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); pipe_ctx 57 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); pipe_ctx 810 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c const struct pipe_ctx *pipe_ctx, pipe_ctx 813 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 821 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pixel_clk_params->signal_type = pipe_ctx->stream->signal; pipe_ctx 822 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; pipe_ctx 844 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) pipe_ctx 846 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx 847 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx 848 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->clock_source, pipe_ctx 849 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &pipe_ctx->stream_res.pix_clk_params, pipe_ctx 850 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &pipe_ctx->pll_settings); pipe_ctx 851 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c resource_build_bit_depth_reduction_params(pipe_ctx->stream, pipe_ctx 852 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &pipe_ctx->stream->bit_depth_params); pipe_ctx 853 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; pipe_ctx 856 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) pipe_ctx 858 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pipe_ctx->pipe_idx != underlay_idx) pipe_ctx 860 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!pipe_ctx->plane_state) pipe_ctx 862 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) pipe_ctx 872 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); pipe_ctx 874 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!pipe_ctx) pipe_ctx 877 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!is_surface_pixel_format_supported(pipe_ctx, pipe_ctx 881 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_resource_build_pipe_hw_param(pipe_ctx); pipe_ctx 885 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c resource_build_info_frame(pipe_ctx); pipe_ctx 905 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c context->res_ctx.pipe_ctx, pipe_ctx 1048 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static struct pipe_ctx *dce110_acquire_underlay( pipe_ctx 1056 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; pipe_ctx 1058 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (res_ctx->pipe_ctx[underlay_idx].stream) pipe_ctx 1061 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; pipe_ctx 1062 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; pipe_ctx 1064 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; pipe_ctx 1065 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; pipe_ctx 1066 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->pipe_idx = underlay_idx; pipe_ctx 1068 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream = stream; pipe_ctx 1070 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { pipe_ctx 1076 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg->inst, pipe_ctx 1084 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, pipe_ctx 1090 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream->signal, pipe_ctx 1093 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg->funcs->enable_advanced_request( pipe_ctx 1094 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg, pipe_ctx 1098 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, pipe_ctx 1106 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg->funcs->set_blank_color( pipe_ctx 1107 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.tg, pipe_ctx 1111 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return pipe_ctx; pipe_ctx 41 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); pipe_ctx 800 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); pipe_ctx 802 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!pipe_ctx) pipe_ctx 805 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce110_resource_build_pipe_hw_param(pipe_ctx); pipe_ctx 807 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c resource_build_info_frame(pipe_ctx); pipe_ctx 827 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c context->res_ctx.pipe_ctx, pipe_ctx 891 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( pipe_ctx 894 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!pipe_ctx) pipe_ctx 897 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (dc_is_dp_signal(pipe_ctx->stream->signal) pipe_ctx 898 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c || dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx 899 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pipe_ctx->clock_source = pipe_ctx 902 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pipe_ctx->clock_source = find_matching_pll( pipe_ctx 906 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pipe_ctx->clock_source == NULL) pipe_ctx 912 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pipe_ctx->clock_source); pipe_ctx 808 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (context->res_ctx.pipe_ctx[i].stream) pipe_ctx 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 716 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 732 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 736 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 744 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe != NULL) pipe_ctx 752 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); pipe_ctx 754 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx 755 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->clock_source, pipe_ctx 756 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->stream_res.pix_clk_params, pipe_ctx 757 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->pll_settings)) { pipe_ctx 762 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->program_timing( pipe_ctx 763 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 765 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_ctx 766 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_ctx 767 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx 768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_width, pipe_ctx 769 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->signal, pipe_ctx 776 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; pipe_ctx 778 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx 779 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, pipe_ctx 787 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.tg->funcs->set_blank_color) pipe_ctx 788 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_blank_color( pipe_ctx 789 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 792 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.tg->funcs->is_blanked && pipe_ctx 793 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) { pipe_ctx 794 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); pipe_ctx 795 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg); pipe_ctx 796 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg); pipe_ctx 800 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { pipe_ctx 818 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 823 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx 824 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream = NULL; pipe_ctx 830 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->stream->dpms_off) pipe_ctx 831 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c core_link_disable_stream(pipe_ctx); pipe_ctx 832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c else if (pipe_ctx->stream_res.audio) pipe_ctx 833 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.disable_audio_stream(pipe_ctx); pipe_ctx 835 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.audio) { pipe_ctx 837 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); pipe_ctx 844 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.audio, false); pipe_ctx 845 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.audio = NULL; pipe_ctx 854 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe == NULL) { pipe_ctx 855 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx 857 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); pipe_ctx 858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.tg->funcs->set_drr) pipe_ctx 859 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_drr( pipe_ctx 860 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, NULL); pipe_ctx 864 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) pipe_ctx 870 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream = NULL; pipe_ctx 872 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); pipe_ctx 885 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = pipe_ctx 886 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 887 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx != NULL) { pipe_ctx 888 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; pipe_ctx 910 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = pipe_ctx 911 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 912 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx != NULL) { pipe_ctx 913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; pipe_ctx 923 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = pipe_ctx 924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 925 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx != NULL) { pipe_ctx 926 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; pipe_ctx 933 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = pipe_ctx 934 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 935 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx != NULL) { pipe_ctx 936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; pipe_ctx 945 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = pipe_ctx 946 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 947 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx != NULL) { pipe_ctx 948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; pipe_ctx 977 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 979 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 980 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int dpp_id = pipe_ctx->plane_res.dpp->inst; pipe_ctx 984 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; pipe_ctx 995 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; pipe_ctx 1029 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; pipe_ctx 1035 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); pipe_ctx 1041 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) pipe_ctx 1042 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( pipe_ctx 1043 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, pipe_ctx 1050 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, pipe_ctx 1051 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp); pipe_ctx 1053 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream = NULL; pipe_ctx 1054 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); pipe_ctx 1055 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); pipe_ctx 1056 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->top_pipe = NULL; pipe_ctx 1057 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->bottom_pipe = NULL; pipe_ctx 1058 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_state = NULL; pipe_ctx 1061 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1065 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) pipe_ctx 1068 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.plane_atomic_disable(dc, pipe_ctx); pipe_ctx 1073 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_idx); pipe_ctx 1090 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1096 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream != NULL && can_apply_seamless_boot) pipe_ctx 1115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream != NULL && can_apply_seamless_boot) pipe_ctx 1129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream != NULL && pipe_ctx 1137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->is_tg_enabled( pipe_ctx 1138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg)) pipe_ctx 1142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg = tg; pipe_ctx 1147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_idx = i; pipe_ctx 1149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp = hubp; pipe_ctx 1150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp = dpp; pipe_ctx 1151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.mpcc_inst = dpp->inst; pipe_ctx 1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; pipe_ctx 1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; pipe_ctx 1161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.plane_atomic_disconnect(dc, pipe_ctx); pipe_ctx 1166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.disable_plane(dc, pipe_ctx); pipe_ctx 1168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg = NULL; pipe_ctx 1169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp = NULL; pipe_ctx 1313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx_old = pipe_ctx 1314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->stream || pipe_ctx 1324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { pipe_ctx 1329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.enable_stream_gating(dc, pipe_ctx); pipe_ctx 1337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) pipe_ctx 1339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 1340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool sec_split = pipe_ctx->top_pipe && pipe_ctx 1341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; pipe_ctx 1343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c (pipe_ctx->stream->timing.timing_3d_format == pipe_ctx 1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->timing.timing_3d_format == pipe_ctx 1352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && pipe_ctx 1364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 1373 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); pipe_ctx 1375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx 1376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp, pipe_ctx 1386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; pipe_ctx 1389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 1392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; pipe_ctx 1468 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; pipe_ctx 1507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe, pipe_ctx 1569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *grouped_pipes[]) pipe_ctx 1598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *grouped_pipes[]) pipe_ctx 1827 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 1839 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->inst); pipe_ctx 1842 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); pipe_ctx 1845 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( pipe_ctx 1846 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, pipe_ctx 1887 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp); pipe_ctx 1894 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) pipe_ctx 1902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { pipe_ctx 1906 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->gamut_remap_matrix.matrix[i]; pipe_ctx 1909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); pipe_ctx 1913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace) pipe_ctx 1915 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) { pipe_ctx 1916 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe) { pipe_ctx 1917 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *top = pipe_ctx->top_pipe; pipe_ctx 1928 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix) pipe_ctx 1936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); pipe_ctx 1943 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 1948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { pipe_ctx 1949 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) { pipe_ctx 1962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) { pipe_ctx 1963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix); pipe_ctx 1965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); pipe_ctx 1969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL) pipe_ctx 1970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); pipe_ctx 1974 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) pipe_ctx 1976 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) pipe_ctx 1978 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) pipe_ctx 1983 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) pipe_ctx 1985 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) pipe_ctx 1987 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) pipe_ctx 1992 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) pipe_ctx 1994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) pipe_ctx 1996 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) pipe_ctx 1998 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) pipe_ctx 2026 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const struct pipe_ctx *pipe_ctx, pipe_ctx 2031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c switch (pipe_ctx->plane_res.scl_data.format) { pipe_ctx 2062 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 2068 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *top_pipe_ctx = pipe_ctx; pipe_ctx 2183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 2185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 2187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; pipe_ctx 2191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); pipe_ctx 2195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx, &blnd_cfg.black_color); pipe_ctx 2198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx, &blnd_cfg.black_color); pipe_ctx 2201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc, pipe_ctx->stream->output_color_space, pipe_ctx 2213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state->global_alpha) pipe_ctx 2214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; pipe_ctx 2222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->output_color_space) pipe_ctx 2237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->plane_state->update_flags.bits.full_update) { pipe_ctx 2263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; pipe_ctx 2267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void update_scaler(struct pipe_ctx *pipe_ctx) pipe_ctx 2270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; pipe_ctx 2272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; pipe_ctx 2273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; pipe_ctx 2275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( pipe_ctx 2276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); pipe_ctx 2281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 2284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 2285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; pipe_ctx 2286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 2307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.bw.dppclk_khz, pipe_ctx 2320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); pipe_ctx 2324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->dlg_regs, pipe_ctx 2325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->ttu_regs, pipe_ctx 2326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->rq_regs, pipe_ctx 2327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->pipe_dlg_param); pipe_ctx 2330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->dlg_regs, pipe_ctx 2331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->ttu_regs); pipe_ctx 2334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c size.surface_size = pipe_ctx->plane_res.scl_data.viewport; pipe_ctx 2343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.update_mpcc(dc, pipe_ctx); pipe_ctx 2350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c update_scaler(pipe_ctx); pipe_ctx 2358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->plane_res.scl_data.viewport, pipe_ctx 2359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->plane_res.scl_data.viewport_c); pipe_ctx 2362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { pipe_ctx 2363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.set_cursor_position(pipe_ctx); pipe_ctx 2364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.set_cursor_attribute(pipe_ctx); pipe_ctx 2367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.set_cursor_sdr_white_level(pipe_ctx); pipe_ctx 2372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.program_gamut_remap(pipe_ctx); pipe_ctx 2375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx, pipe_ctx 2376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->output_color_space, pipe_ctx 2377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->csc_color_matrix.matrix, pipe_ctx 2378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->inst); pipe_ctx 2403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.update_plane_addr(dc, pipe_ctx); pipe_ctx 2405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (is_pipe_tree_visible(pipe_ctx)) pipe_ctx 2411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 2416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct stream_resource *stream_res = &pipe_ctx->stream_res; pipe_ctx 2417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void set_hdr_multiplier(struct pipe_ctx *pipe_ctx) pipe_ctx 2455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_state->sdr_white_level, 80); pipe_ctx 2463 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state->sdr_white_level > 80) pipe_ctx 2466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier( pipe_ctx 2467 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, hw_mult); pipe_ctx 2472 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 2475 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state->update_flags.bits.full_update) pipe_ctx 2476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dcn10_enable_plane(dc, pipe_ctx, context); pipe_ctx 2478 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c update_dchubp_dpp(dc, pipe_ctx, context); pipe_ctx 2480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c set_hdr_multiplier(pipe_ctx); pipe_ctx 2482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state->update_flags.bits.full_update || pipe_ctx 2483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || pipe_ctx 2484 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_state->update_flags.bits.gamma_change) pipe_ctx 2485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); pipe_ctx 2493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state->update_flags.bits.full_update) pipe_ctx 2494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); pipe_ctx 2499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 2502 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe == NULL) { pipe_ctx 2503 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool blank = !is_pipe_tree_visible(pipe_ctx); pipe_ctx 2505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->program_global_sync( pipe_ctx 2506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 2507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_ctx 2508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_ctx 2509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx 2510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_width); pipe_ctx 2512 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->set_vtg_params( pipe_ctx 2513 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); pipe_ctx 2515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); pipe_ctx 2519 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state != NULL) pipe_ctx 2520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dcn10_program_pipe(dc, pipe_ctx, context); pipe_ctx 2522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) pipe_ctx 2523 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); pipe_ctx 2526 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *find_top_pipe_for_stream( pipe_ctx 2534 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *old_pipe_ctx = pipe_ctx 2536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2538 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) pipe_ctx 2541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream != stream) pipe_ctx 2544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) pipe_ctx 2545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c return pipe_ctx; pipe_ctx 2561 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *top_pipe_to_program = pipe_ctx 2596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *old_pipe_ctx = pipe_ctx 2598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 2605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { pipe_ctx 2612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if ((!pipe_ctx->plane_state || pipe_ctx 2613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) && pipe_ctx 2635 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2637 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->stream || pipe_ctx->stream == stream || pipe_ctx 2638 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg)) pipe_ctx 2641 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( pipe_ctx 2642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp, pipe_ctx 2643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->dlg_regs, pipe_ctx 2644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->ttu_regs); pipe_ctx 2657 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); pipe_ctx 2749 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_set_drr(struct pipe_ctx **pipe_ctx, pipe_ctx 2768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs->set_drr( pipe_ctx 2769 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx[i]->stream_res.tg, ¶ms); pipe_ctx 2771 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( pipe_ctx 2772 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx[i]->stream_res.tg, pipe_ctx 2777 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_get_position(struct pipe_ctx **pipe_ctx, pipe_ctx 2786 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); pipe_ctx 2789 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, pipe_ctx 2803 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx[i]->stream_res.tg->funcs-> pipe_ctx 2804 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); pipe_ctx 2844 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) pipe_ctx 2847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_program_stereo( pipe_ctx 2859 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, pipe_ctx 2863 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->program_stereo( pipe_ctx 2864 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, pipe_ctx 2886 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx) pipe_ctx 2894 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->stream_res.opp) pipe_ctx 2898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { pipe_ctx 2902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; pipe_ctx 2922 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) pipe_ctx 2924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 2925 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 2931 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending( pipe_ctx 2932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp); pipe_ctx 2942 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); pipe_ctx 2954 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) pipe_ctx 2956 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; pipe_ctx 2957 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 2958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; pipe_ctx 2960 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, pipe_ctx 2961 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz, pipe_ctx 2962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .viewport = pipe_ctx->plane_res.scl_data.viewport, pipe_ctx 2963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, pipe_ctx 2964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, pipe_ctx 2965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .rotation = pipe_ctx->plane_state->rotation, pipe_ctx 2966 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .mirror = pipe_ctx->plane_state->horizontal_mirror pipe_ctx 2968 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x; pipe_ctx 2969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y; pipe_ctx 2978 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_state->address.type pipe_ctx 2985 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width - pipe_ctx 2986 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x; pipe_ctx 2992 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pos_cpy.x > pipe_ctx->plane_res.scl_data.viewport.height) { pipe_ctx 2993 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height; pipe_ctx 2994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x; pipe_ctx 2996 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x; pipe_ctx 3002 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) { pipe_ctx 3003 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width pipe_ctx 3004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x; pipe_ctx 3007 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x; pipe_ctx 3008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width pipe_ctx 3009 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c || pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) { pipe_ctx 3010 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width; pipe_ctx 3013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y; pipe_ctx 3020 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx) pipe_ctx 3022 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; pipe_ctx 3024 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( pipe_ctx 3025 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp, attributes); pipe_ctx 3026 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( pipe_ctx 3027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, attributes); pipe_ctx 3030 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx) pipe_ctx 3032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level; pipe_ctx 3038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes) pipe_ctx 3053 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes( pipe_ctx 3054 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, &opt_attr); pipe_ctx 3075 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx) pipe_ctx 3077 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing; pipe_ctx 3099 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vstartup_start + 1; pipe_ctx 3108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx; pipe_ctx 3113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 3114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c tg = pipe_ctx->stream_res.tg; pipe_ctx 3119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->top_pipe || pipe_ctx 3120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c !pipe_ctx->stream || !pipe_ctx->plane_state || pipe_ctx 3132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 3136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing; pipe_ctx 3138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->periodic_interrupt0.lines_offset; pipe_ctx 3139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx); pipe_ctx 3161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 3169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point; pipe_ctx 3171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point; pipe_ctx 3176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx, pipe_ctx 3190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct pipe_ctx *pipe_ctx, pipe_ctx 3193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 3199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c cal_vline_position(pipe_ctx, vline, &start_line, &end_line); pipe_ctx 3204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1( pipe_ctx 3206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->periodic_interrupt1.lines_offset); pipe_ctx 3210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) pipe_ctx 3212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 3213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int start_line = get_vupdate_offset_from_vsync(pipe_ctx); pipe_ctx 3224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, pipe_ctx 3228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 3232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c params.timing = pipe_ctx->stream->timing; pipe_ctx 3236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) { pipe_ctx 3239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); pipe_ctx 3247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx, pipe_ctx 3251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) { pipe_ctx 3252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message( pipe_ctx 3253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.stream_enc, pipe_ctx 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx); pipe_ctx 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx); pipe_ctx 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx); pipe_ctx 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void set_hdr_multiplier(struct pipe_ctx *pipe_ctx); pipe_ctx 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h const struct pipe_ctx *pipe_ctx, pipe_ctx 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h struct pipe_ctx *find_top_pipe_for_stream( pipe_ctx 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx); pipe_ctx 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10; pipe_ctx 986 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c const struct pipe_ctx *pipe_ctx, pipe_ctx 989 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 992 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pixel_clk_params->signal_type = pipe_ctx->stream->signal; pipe_ctx 993 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; pipe_ctx 1020 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) pipe_ctx 1023 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx 1025 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx 1026 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pipe_ctx->clock_source, pipe_ctx 1027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &pipe_ctx->stream_res.pix_clk_params, pipe_ctx 1028 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &pipe_ctx->pll_settings); pipe_ctx 1030 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; pipe_ctx 1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c resource_build_bit_depth_reduction_params(pipe_ctx->stream, pipe_ctx 1033 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &pipe_ctx->stream->bit_depth_params); pipe_ctx 1034 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c build_clamping_params(pipe_ctx->stream); pipe_ctx 1042 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); pipe_ctx 1062 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!pipe_ctx) pipe_ctx 1065 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c build_pipe_hw_param(pipe_ctx); pipe_ctx 1088 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( pipe_ctx 1094 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); pipe_ctx 1095 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); pipe_ctx 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { pipe_ctx 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( pipe_ctx 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, pipe_ctx 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp = pipe_ctx->plane_res.dpp; pipe_ctx 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); pipe_ctx 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.gsl_group != 0) pipe_ctx 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); pipe_ctx 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.set_flip_control_gsl(pipe_ctx, false); pipe_ctx 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.dpp, pipe_ctx 499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp); pipe_ctx 501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream = NULL; pipe_ctx 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); pipe_ctx 503 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); pipe_ctx 504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->top_pipe = NULL; pipe_ctx 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->bottom_pipe = NULL; pipe_ctx 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_state = NULL; pipe_ctx 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 514 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) pipe_ctx 517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_plane_atomic_disable(dc, pipe_ctx); pipe_ctx 520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_idx); pipe_ctx 524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 531 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *odm_pipe; pipe_ctx 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; pipe_ctx 539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->top_pipe != NULL) pipe_ctx 544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx 551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, pipe_ctx 553 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->stream->timing); pipe_ctx 558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); pipe_ctx 560 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx 561 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->clock_source, pipe_ctx 562 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->stream_res.pix_clk_params, pipe_ctx 563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->pll_settings)) { pipe_ctx 568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->program_timing( pipe_ctx 569 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, pipe_ctx 571 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_ctx 572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_ctx 573 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx 574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_width, pipe_ctx 575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream->signal, pipe_ctx 578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( pipe_ctx 584 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp, pipe_ctx 587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.blank_pixel_data(dc, pipe_ctx, true); pipe_ctx 590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { pipe_ctx 595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp); pipe_ctx 601 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.tg->funcs->set_drr) pipe_ctx 602 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_drr( pipe_ctx 603 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, ¶ms); pipe_ctx 608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) pipe_ctx 609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx 610 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, event_triggers); pipe_ctx 624 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id = pipe_ctx->plane_res.hubp->inst; pipe_ctx 636 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { pipe_ctx 651 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id = pipe_ctx->plane_res.hubp->inst; pipe_ctx 655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; pipe_ctx 666 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->top_pipe == NULL pipe_ctx 670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c else if (pipe_ctx->stream->out_transfer_func->type == pipe_ctx 691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) pipe_ctx 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; pipe_ctx 713 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) pipe_ctx 715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; pipe_ctx 749 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; pipe_ctx 760 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_set_shaper_3dlut(pipe_ctx, plane_state); pipe_ctx 761 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_set_blend_lut(pipe_ctx, plane_state); pipe_ctx 826 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) pipe_ctx 828 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *odm_pipe; pipe_ctx 830 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; pipe_ctx 832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 838 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx 839 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, pipe_ctx 841 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->stream->timing); pipe_ctx 843 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx 844 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); pipe_ctx 849 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 853 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct stream_resource *stream_res = &pipe_ctx->stream_res; pipe_ctx 854 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 857 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *odm_pipe; pipe_ctx 866 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 889 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 910 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx) pipe_ctx 916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); pipe_ctx 917 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); pipe_ctx 921 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); pipe_ctx 927 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 933 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_power_on_plane(dc->hwseq, pipe_ctx); pipe_ctx 936 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); pipe_ctx 939 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); pipe_ctx 942 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( pipe_ctx 943 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp, pipe_ctx 992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); pipe_ctx 1003 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 1006 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_state->update_flags.bits.full_update = pipe_ctx 1007 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update; pipe_ctx 1009 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state->update_flags.bits.full_update) pipe_ctx 1010 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_enable_plane(dc, pipe_ctx, context); pipe_ctx 1012 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c update_dchubp_dpp(dc, pipe_ctx, context); pipe_ctx 1014 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c set_hdr_multiplier(pipe_ctx); pipe_ctx 1016 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state->update_flags.bits.full_update || pipe_ctx 1017 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || pipe_ctx 1018 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_state->update_flags.bits.gamma_change) pipe_ctx 1019 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); pipe_ctx 1027 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state->update_flags.bits.full_update) pipe_ctx 1028 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); pipe_ctx 1033 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 1036 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) { pipe_ctx 1037 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool blank = !is_pipe_tree_visible(pipe_ctx); pipe_ctx 1039 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->program_global_sync( pipe_ctx 1040 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, pipe_ctx 1041 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_ctx 1042 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_ctx 1043 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx 1044 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_width); pipe_ctx 1046 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_vtg_params( pipe_ctx 1047 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); pipe_ctx 1049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); pipe_ctx 1052 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.update_odm(dc, context, pipe_ctx); pipe_ctx 1055 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state != NULL) pipe_ctx 1056 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_program_pipe(dc, pipe_ctx, context); pipe_ctx 1058 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->bottom_pipe != NULL) { pipe_ctx 1059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ASSERT(pipe_ctx->bottom_pipe != pipe_ctx); pipe_ctx 1060 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); pipe_ctx 1061 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c } else if (pipe_ctx->next_odm_pipe != NULL) { pipe_ctx 1062 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx); pipe_ctx 1063 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context); pipe_ctx 1069 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe, pipe_ctx 1091 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe, pipe_ctx 1156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *top_pipe_to_program = pipe_ctx 1158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *prev_top_pipe_to_program = pipe_ctx 1167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *old_pipe_ctx = pipe_ctx 1169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream == stream && pipe_ctx 1172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream == old_pipe_ctx->stream) pipe_ctx 1173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.gsl_group = pipe_ctx 1194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *old_pipe_ctx = pipe_ctx 1196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { pipe_ctx 1210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if ((!pipe_ctx->plane_state || pipe_ctx 1211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) && pipe_ctx 1232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe_ctx->stream || pipe_ctx->stream == stream || pipe_ctx 1236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg)) pipe_ctx 1239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( pipe_ctx 1240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, pipe_ctx 1241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->dlg_regs, pipe_ctx 1242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->ttu_regs); pipe_ctx 1252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); pipe_ctx 1323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state == NULL) pipe_ctx 1328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->top_pipe == NULL) { pipe_ctx 1329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool blank = !is_pipe_tree_visible(pipe_ctx); pipe_ctx 1331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->program_global_sync( pipe_ctx 1332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, pipe_ctx 1333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_ctx 1334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_ctx 1335 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx 1336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_width); pipe_ctx 1338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_vtg_params( pipe_ctx 1339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); pipe_ctx 1340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->prev_odm_pipe == NULL) pipe_ctx 1341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); pipe_ctx 1344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_setup( pipe_ctx 1345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, pipe_ctx 1346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->dlg_regs, pipe_ctx 1347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->ttu_regs, pipe_ctx 1348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->rq_regs, pipe_ctx 1349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->pipe_dlg_param); pipe_ctx 1419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) pipe_ctx 1421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 1428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.dsc) { pipe_ctx 1434 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; pipe_ctx 1436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); pipe_ctx 1445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.dsc) { pipe_ctx 1451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; pipe_ctx 1453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); pipe_ctx 1462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) pipe_ctx 1465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 1469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; pipe_ctx 1471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream->dmdata_address.quad_part; pipe_ctx 1482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 1484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dce110_disable_stream(pipe_ctx); pipe_ctx 1528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) pipe_ctx 1530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 1531 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool sec_split = pipe_ctx->top_pipe && pipe_ctx 1532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; pipe_ctx 1534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c (pipe_ctx->stream->timing.timing_3d_format == pipe_ctx 1536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream->timing.timing_3d_format == pipe_ctx 1544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && pipe_ctx 1554 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_plane_state *plane_state = pipe_ctx->plane_state; pipe_ctx 1563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); pipe_ctx 1566 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); pipe_ctx 1568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx 1569 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, pipe_ctx 1579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; pipe_ctx 1582 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, pipe_ctx 1586 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1588 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *odm_pipe; pipe_ctx 1591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { pipe_ctx 1595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c params.timing = pipe_ctx->stream->timing; pipe_ctx 1599 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) { pipe_ctx 1602 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( pipe_ctx 1603 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); pipe_ctx 1604 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); pipe_ctx 1612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) pipe_ctx 1614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 1615 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int start_line = get_vupdate_offset_from_vsync(pipe_ctx); pipe_ctx 1626 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 1631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx 1632 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream = NULL; pipe_ctx 1638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe_ctx->stream->dpms_off) pipe_ctx 1639 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c core_link_disable_stream(pipe_ctx); pipe_ctx 1640 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c else if (pipe_ctx->stream_res.audio) pipe_ctx 1641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.disable_audio_stream(pipe_ctx); pipe_ctx 1644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.audio) { pipe_ctx 1646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); pipe_ctx 1653 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.audio, false); pipe_ctx 1654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.audio = NULL; pipe_ctx 1659 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c else if (pipe_ctx->stream_res.dsc) { pipe_ctx 1660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dp_set_dsc_enable(pipe_ctx, false); pipe_ctx 1668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->top_pipe == NULL) { pipe_ctx 1669 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx 1671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); pipe_ctx 1672 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) pipe_ctx 1673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx 1674 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); pipe_ctx 1676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.tg->funcs->set_drr) pipe_ctx 1677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_drr( pipe_ctx 1678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, NULL); pipe_ctx 1682 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) pipe_ctx 1688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream = NULL; pipe_ctx 1690 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); pipe_ctx 1701 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx_old = pipe_ctx 1702 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dc->current_state->res_ctx.pipe_ctx[i]; pipe_ctx 1703 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 1711 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe_ctx->stream || pipe_ctx 1712 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { pipe_ctx 1717 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.enable_stream_gating(dc, pipe_ctx); pipe_ctx 1724 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx 1726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 1728 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; pipe_ctx 1732 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); pipe_ctx 1737 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx, &blnd_cfg.black_color); pipe_ctx 1740 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx, &blnd_cfg.black_color); pipe_ctx 1751 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_state->global_alpha) pipe_ctx 1752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; pipe_ctx 1774 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe_ctx->plane_state->update_flags.bits.full_update) { pipe_ctx 1799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; pipe_ctx 1832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 1844 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.gsl_group > 0) pipe_ctx 1849 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.gsl_group = group_idx; pipe_ctx 1871 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c group_idx = pipe_ctx->stream_res.gsl_group; pipe_ctx 1875 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.gsl_group = 0; pipe_ctx 1899 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && pipe_ctx 1900 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { pipe_ctx 1901 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_gsl( pipe_ctx 1902 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, pipe_ctx 1905 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( pipe_ctx 1906 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); pipe_ctx 1912 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx, pipe_ctx 1915 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) pipe_ctx 1916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( pipe_ctx 1917 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, flip_immediate); pipe_ctx 1921 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx 1924 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream->link->cur_link_settings.lane_count; pipe_ctx 1926 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; pipe_ctx 1927 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_link *link = pipe_ctx->stream->link; pipe_ctx 1931 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct timing_generator *tg = pipe_ctx->stream_res.tg; pipe_ctx 1939 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.stream_enc->id, true); pipe_ctx 1942 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c link->dc->hwss.program_dmdata_engine(pipe_ctx); pipe_ctx 1944 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c link->dc->hwss.update_info_frame(pipe_ctx); pipe_ctx 1961 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.audio != NULL) { pipe_ctx 1962 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx 1963 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); pipe_ctx 1967 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) pipe_ctx 1969 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1970 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; pipe_ctx 1972 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; pipe_ctx 1978 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream->dmdata_address.quad_part != 0) { pipe_ctx 1979 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; pipe_ctx 2057 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2061 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg = tg; pipe_ctx 2062 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_idx = i; pipe_ctx 2064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp = hubp; pipe_ctx 2065 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.dpp = dpp; pipe_ctx 2066 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.mpcc_inst = dpp->inst; pipe_ctx 2070 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp = NULL; pipe_ctx 2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; pipe_ctx 2077 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; pipe_ctx 2079 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hwss1_plane_atomic_disconnect(dc, pipe_ctx); pipe_ctx 2094 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2096 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->hwss.disable_plane(dc, pipe_ctx); pipe_ctx 2098 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg = NULL; pipe_ctx 2099 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp = NULL; pipe_ctx 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct pipe_ctx *pipe_ctx, pipe_ctx 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct pipe_ctx *pipe_ctx, pipe_ctx 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct pipe_ctx *pipe_ctx, pipe_ctx 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx, pipe_ctx 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx); pipe_ctx 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx); pipe_ctx 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_disable_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct pipe_ctx *pipe_ctx, pipe_ctx 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx); pipe_ctx 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct pipe_ctx *pipe, pipe_ctx 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct pipe_ctx *pipe_ctx, pipe_ctx 1435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe_ctx, pipe_ctx 1438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c const struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 1439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *odm_pipe; pipe_ctx 1442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 1447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pixel_clk_params->signal_type = pipe_ctx->stream->signal; pipe_ctx 1448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; pipe_ctx 1478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) pipe_ctx 1481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx 1483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx 1484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_ctx->clock_source, pipe_ctx 1485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &pipe_ctx->stream_res.pix_clk_params, pipe_ctx 1486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &pipe_ctx->pll_settings); pipe_ctx 1488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; pipe_ctx 1490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c resource_build_bit_depth_reduction_params(pipe_ctx->stream, pipe_ctx 1491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &pipe_ctx->stream->bit_depth_params); pipe_ctx 1492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c build_clamping_params(pipe_ctx->stream); pipe_ctx 1500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); pipe_ctx 1520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx) pipe_ctx 1524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c status = build_pipe_hw_param(pipe_ctx); pipe_ctx 1584 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; pipe_ctx 1586 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pipe_ctx->stream != dc_stream) pipe_ctx 1589 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i); pipe_ctx 1592 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx->stream_res.dsc) { pipe_ctx 1608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe_ctx = NULL; pipe_ctx 1612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { pipe_ctx 1613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; pipe_ctx 1615 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pipe_ctx->stream_res.dsc) pipe_ctx 1616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); pipe_ctx 1620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx) pipe_ctx 1725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *prev_odm_pipe, pipe_ctx 1726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *next_odm_pipe) pipe_ctx 1803 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *primary_pipe, pipe_ctx 1804 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *secondary_pipe) pipe_ctx 1807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; pipe_ctx 1841 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; pipe_ctx 1843 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!res_ctx->pipe_ctx[i].stream) pipe_ctx 1879 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!res_ctx->pipe_ctx[i].stream) pipe_ctx 1887 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[pipe_cnt].stream, pipe_ctx 1888 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].stream)) { pipe_ctx 1895 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; pipe_ctx 1898 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!res_ctx->pipe_ctx[i].stream) pipe_ctx 1906 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; pipe_ctx 1908 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; pipe_ctx 1910 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { pipe_ctx 1918 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; pipe_ctx 1941 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; pipe_ctx 1943 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; pipe_ctx 1944 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; pipe_ctx 1945 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe pipe_ctx 1946 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c || res_ctx->pipe_ctx[i].next_odm_pipe; pipe_ctx 1947 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; pipe_ctx 1948 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state pipe_ctx 1949 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c == res_ctx->pipe_ctx[i].plane_state) pipe_ctx 1950 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; pipe_ctx 1951 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { pipe_ctx 1952 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; pipe_ctx 1959 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c switch (res_ctx->pipe_ctx[i].stream->signal) { pipe_ctx 1978 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { pipe_ctx 2010 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { pipe_ctx 2044 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!res_ctx->pipe_ctx[i].plane_state) { pipe_ctx 2071 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; pipe_ctx 2072 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; pipe_ctx 2075 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe pipe_ctx 2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) pipe_ctx 2077 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c || (res_ctx->pipe_ctx[i].top_pipe pipe_ctx 2078 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln); pipe_ctx 2101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) { pipe_ctx 2103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width; pipe_ctx 2105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height; pipe_ctx 2106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) { pipe_ctx 2108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; pipe_ctx 2110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height; pipe_ctx 2213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 2217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) pipe_ctx 2223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { pipe_ctx 2224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) pipe_ctx 2235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ pipe_ctx 2259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; pipe_ctx 2260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_stream_state *stream = pipe_ctx->stream; pipe_ctx 2262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *odm_pipe; pipe_ctx 2265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) pipe_ctx 2269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) pipe_ctx 2281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) pipe_ctx 2288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, pipe_ctx 2291 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c const struct pipe_ctx *primary_pipe) pipe_ctx 2293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *secondary_pipe = NULL; pipe_ctx 2306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { pipe_ctx 2307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; pipe_ctx 2308 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { pipe_ctx 2309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; pipe_ctx 2312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { pipe_ctx 2313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; pipe_ctx 2314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { pipe_ctx 2315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; pipe_ctx 2328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) { pipe_ctx 2331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { pipe_ctx 2332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; pipe_ctx 2352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { pipe_ctx 2353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; pipe_ctx 2390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; pipe_ctx 2398 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; pipe_ctx 2421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; pipe_ctx 2487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 2527 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_ctx 2528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; pipe_ctx 2638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 2763 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 2799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 2803 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipe_ctx 2806 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; pipe_ctx 2818 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 2822 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &context->res_ctx.pipe_ctx[i].dlg_regs, pipe_ctx 2823 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &context->res_ctx.pipe_ctx[i].ttu_regs, pipe_ctx 2832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &context->res_ctx.pipe_ctx[i].rq_regs, pipe_ctx 2934 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( pipe_ctx 2940 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); pipe_ctx 2941 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); pipe_ctx 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( pipe_ctx 994 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!context->res_ctx.pipe_ctx[i].stream) pipe_ctx 78 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx *pipe_ctx); pipe_ctx 80 drivers/gpu/drm/amd/display/dc/inc/core_types.h void core_link_disable_stream(struct pipe_ctx *pipe_ctx); pipe_ctx 82 drivers/gpu/drm/amd/display/dc/inc/core_types.h void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); pipe_ctx 113 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx *(*acquire_idle_pipe_for_layer)( pipe_ctx 301 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx *top_pipe; pipe_ctx 302 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx *bottom_pipe; pipe_ctx 303 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx *next_odm_pipe; pipe_ctx 304 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx *prev_odm_pipe; pipe_ctx 320 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pipe_ctx pipe_ctx[MAX_PIPES]; pipe_ctx 76 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); pipe_ctx 77 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable); pipe_ctx 78 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); pipe_ctx 79 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); pipe_ctx 35 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct pipe_ctx; pipe_ctx 484 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h const struct pipe_ctx *pipe, pipe_ctx 42 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h struct pipe_ctx; pipe_ctx 67 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx; pipe_ctx 87 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 89 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 108 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx); pipe_ctx 111 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 119 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 122 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 128 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx); pipe_ctx 132 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx); pipe_ctx 151 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx); pipe_ctx 154 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx); pipe_ctx 157 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 161 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 172 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *grouped_pipes[]); pipe_ctx 177 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *grouped_pipes[]); pipe_ctx 189 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 191 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*update_info_frame)(struct pipe_ctx *pipe_ctx); pipe_ctx 194 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 198 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*enable_stream)(struct pipe_ctx *pipe_ctx); pipe_ctx 200 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*disable_stream)(struct pipe_ctx *pipe_ctx); pipe_ctx 202 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*unblank_stream)(struct pipe_ctx *pipe_ctx, pipe_ctx 205 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*blank_stream)(struct pipe_ctx *pipe_ctx); pipe_ctx 207 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); pipe_ctx 209 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); pipe_ctx 213 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe, pipe_ctx 218 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe, pipe_ctx 222 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 236 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); pipe_ctx 237 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); pipe_ctx 240 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, pipe_ctx 244 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, pipe_ctx 247 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, pipe_ctx 251 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 256 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx, pipe_ctx 259 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); pipe_ctx 268 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct pipe_ctx *pipe_ctx); pipe_ctx 278 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*set_cursor_position)(struct pipe_ctx *pipe); pipe_ctx 279 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*set_cursor_attribute)(struct pipe_ctx *pipe); pipe_ctx 280 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); pipe_ctx 282 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline); pipe_ctx 283 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx); pipe_ctx 284 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 294 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct dc *dc, struct pipe_ctx *pipe_ctx); pipe_ctx 317 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); pipe_ctx 94 drivers/gpu/drm/amd/display/dc/inc/resource.h bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); pipe_ctx 100 drivers/gpu/drm/amd/display/dc/inc/resource.h void resource_build_info_frame(struct pipe_ctx *pipe_ctx); pipe_ctx 123 drivers/gpu/drm/amd/display/dc/inc/resource.h struct pipe_ctx *pipe_ctx); pipe_ctx 129 drivers/gpu/drm/amd/display/dc/inc/resource.h struct pipe_ctx *resource_get_head_pipe_for_stream( pipe_ctx 140 drivers/gpu/drm/amd/display/dc/inc/resource.h struct pipe_ctx *find_idle_secondary_pipe( pipe_ctx 143 drivers/gpu/drm/amd/display/dc/inc/resource.h const struct pipe_ctx *primary_pipe); pipe_ctx 170 drivers/gpu/drm/amd/display/dc/inc/resource.h struct pipe_ctx *pipe_ctx_old, pipe_ctx 171 drivers/gpu/drm/amd/display/dc/inc/resource.h struct pipe_ctx *pipe_ctx); pipe_ctx 215 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;