CREG_AXI_M_OFT0   226 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
CREG_AXI_M_OFT0   232 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
CREG_AXI_M_OFT0   251 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
CREG_AXI_M_OFT0   257 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
CREG_AXI_M_OFT0   263 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
CREG_AXI_M_OFT0   269 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
CREG_AXI_M_OFT0   275 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
CREG_AXI_M_OFT0   281 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
CREG_AXI_M_OFT0   287 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
CREG_AXI_M_OFT0   293 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
CREG_AXI_M_OFT0   299 arch/arc/plat-hsdk/platform.c 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
CREG_AXI_M_OFT0   305 arch/arc/plat-hsdk/platform.c 	writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));