phy_set_bits 2306 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x15, BIT(8)); phy_set_bits 2310 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x06, BIT(13)); phy_set_bits 3248 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); phy_set_bits 3698 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x14, BIT(8)); phy_set_bits 3774 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x14, BIT(8)); phy_set_bits 332 drivers/net/phy/adin.c return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, phy_set_bits 449 drivers/net/phy/adin.c return phy_set_bits(phydev, ADIN1300_INT_MASK_REG, phy_set_bits 1110 drivers/net/phy/marvell.c return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3, phy_set_bits 105 drivers/net/phy/nxp-tja11xx.c return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); phy_set_bits 110 drivers/net/phy/nxp-tja11xx.c return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); phy_set_bits 125 drivers/net/phy/nxp-tja11xx.c ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); phy_set_bits 193 drivers/net/phy/nxp-tja11xx.c ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); phy_set_bits 1999 drivers/net/phy/phy_device.c return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); phy_set_bits 168 drivers/net/phy/realtek.c return phy_set_bits(phydev, MII_CTRL1000, phy_set_bits 276 drivers/net/phy/realtek.c ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,