phy_set_bb_reg    156 drivers/staging/rtl8188eu/hal/bb_cfg.c 			phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
phy_set_bb_reg    374 drivers/staging/rtl8188eu/hal/bb_cfg.c 		phy_set_bb_reg(adapt, addr, bMaskDWord, data);
phy_set_bb_reg    677 drivers/staging/rtl8188eu/hal/bb_cfg.c 	phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
phy_set_bb_reg    300 drivers/staging/rtl8188eu/hal/odm.c 		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
phy_set_bb_reg    517 drivers/staging/rtl8188eu/hal/odm.c 	phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
phy_set_bb_reg    518 drivers/staging/rtl8188eu/hal/odm.c 	phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
phy_set_bb_reg    541 drivers/staging/rtl8188eu/hal/odm.c 	phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
phy_set_bb_reg    542 drivers/staging/rtl8188eu/hal/odm.c 	phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
phy_set_bb_reg    662 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
phy_set_bb_reg    663 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
phy_set_bb_reg    664 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
phy_set_bb_reg    665 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
phy_set_bb_reg    666 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
phy_set_bb_reg    667 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
phy_set_bb_reg    668 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
phy_set_bb_reg    670 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);
phy_set_bb_reg    671 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70);
phy_set_bb_reg    672 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
phy_set_bb_reg    673 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
phy_set_bb_reg    674 drivers/staging/rtl8188eu/hal/odm.c 			phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0);
phy_set_bb_reg     18 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
phy_set_bb_reg     19 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
phy_set_bb_reg     25 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
phy_set_bb_reg     28 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
phy_set_bb_reg     29 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
phy_set_bb_reg     30 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
phy_set_bb_reg     31 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
phy_set_bb_reg     33 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
phy_set_bb_reg     36 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
phy_set_bb_reg     37 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
phy_set_bb_reg     39 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
phy_set_bb_reg     49 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
phy_set_bb_reg     50 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
phy_set_bb_reg     57 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
phy_set_bb_reg     60 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
phy_set_bb_reg     61 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
phy_set_bb_reg     62 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
phy_set_bb_reg     63 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
phy_set_bb_reg     65 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
phy_set_bb_reg     68 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
phy_set_bb_reg     69 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
phy_set_bb_reg     71 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
phy_set_bb_reg     76 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
phy_set_bb_reg     78 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
phy_set_bb_reg     81 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,
phy_set_bb_reg    106 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x4c, bMaskDWord,
phy_set_bb_reg    109 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x7b4, bMaskDWord,
phy_set_bb_reg    113 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);
phy_set_bb_reg    114 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);
phy_set_bb_reg    116 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0);
phy_set_bb_reg    117 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x864, BIT(10), 0);
phy_set_bb_reg    118 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0);
phy_set_bb_reg    119 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1);
phy_set_bb_reg    120 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);
phy_set_bb_reg    124 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1);
phy_set_bb_reg    125 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2);
phy_set_bb_reg    127 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);
phy_set_bb_reg    128 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 		phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);
phy_set_bb_reg    132 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x80c, BIT(21), 1);
phy_set_bb_reg    133 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0);
phy_set_bb_reg    134 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1);
phy_set_bb_reg    137 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
phy_set_bb_reg    138 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 	phy_set_bb_reg(adapter, 0xc50, BIT(7), 1);
phy_set_bb_reg    171 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
phy_set_bb_reg    173 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
phy_set_bb_reg    175 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
phy_set_bb_reg    177 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
phy_set_bb_reg    180 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
phy_set_bb_reg    182 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
phy_set_bb_reg    312 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
phy_set_bb_reg    313 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
phy_set_bb_reg    316 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 				phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
phy_set_bb_reg    325 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1);
phy_set_bb_reg    326 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 			phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
phy_set_bb_reg    329 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c 				phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
phy_set_bb_reg     74 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord,
phy_set_bb_reg     78 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2);
phy_set_bb_reg    106 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);
phy_set_bb_reg    229 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0);
phy_set_bb_reg    230 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0);
phy_set_bb_reg    233 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1);
phy_set_bb_reg    234 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1);
phy_set_bb_reg    238 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand,
phy_set_bb_reg    240 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00,
phy_set_bb_reg    242 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)),
phy_set_bb_reg    532 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
phy_set_bb_reg    533 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
phy_set_bb_reg    534 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
phy_set_bb_reg    535 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
phy_set_bb_reg    538 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
phy_set_bb_reg    541 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
phy_set_bb_reg    542 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
phy_set_bb_reg    565 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
phy_set_bb_reg    575 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
phy_set_bb_reg    578 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
phy_set_bb_reg    579 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
phy_set_bb_reg    582 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
phy_set_bb_reg    583 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
phy_set_bb_reg    584 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
phy_set_bb_reg    585 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
phy_set_bb_reg    588 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
phy_set_bb_reg    591 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
phy_set_bb_reg    592 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
phy_set_bb_reg    610 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, u4tmp);
phy_set_bb_reg    616 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
phy_set_bb_reg    621 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
phy_set_bb_reg    624 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x01004800);
phy_set_bb_reg    627 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
phy_set_bb_reg    628 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
phy_set_bb_reg    629 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
phy_set_bb_reg    630 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
phy_set_bb_reg    633 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
phy_set_bb_reg    635 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
phy_set_bb_reg    636 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
phy_set_bb_reg    647 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
phy_set_bb_reg    668 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
phy_set_bb_reg    669 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
phy_set_bb_reg    712 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, tx0_a);
phy_set_bb_reg    713 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(31),
phy_set_bb_reg    721 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XCTxAFE, 0xF0000000,
phy_set_bb_reg    723 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000,
phy_set_bb_reg    725 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(29),
phy_set_bb_reg    732 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg);
phy_set_bb_reg    735 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg);
phy_set_bb_reg    738 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
phy_set_bb_reg    757 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, tx1_a);
phy_set_bb_reg    759 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(27),
phy_set_bb_reg    768 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, 0xF0000000,
phy_set_bb_reg    770 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000,
phy_set_bb_reg    772 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(25),
phy_set_bb_reg    779 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
phy_set_bb_reg    782 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
phy_set_bb_reg    785 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg);
phy_set_bb_reg    815 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, backup[i]);
phy_set_bb_reg    837 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, 0x0b1b25a0);
phy_set_bb_reg    840 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, path_on);
phy_set_bb_reg    844 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, path_on);
phy_set_bb_reg    861 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x0);
phy_set_bb_reg    862 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, 0x840, bMaskDWord, 0x00010000);
phy_set_bb_reg    863 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
phy_set_bb_reg    871 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
phy_set_bb_reg    872 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
phy_set_bb_reg   1004 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00);
phy_set_bb_reg   1005 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
phy_set_bb_reg   1006 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
phy_set_bb_reg   1007 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
phy_set_bb_reg   1009 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
phy_set_bb_reg   1010 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
phy_set_bb_reg   1011 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
phy_set_bb_reg   1012 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
phy_set_bb_reg   1015 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord,
phy_set_bb_reg   1017 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord,
phy_set_bb_reg   1027 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);
phy_set_bb_reg   1030 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000);
phy_set_bb_reg   1033 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
phy_set_bb_reg   1034 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
phy_set_bb_reg   1035 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
phy_set_bb_reg   1100 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0);
phy_set_bb_reg   1122 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter,
phy_set_bb_reg   1125 drivers/staging/rtl8188eu/hal/phy.c 			phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter,
phy_set_bb_reg   1129 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
phy_set_bb_reg   1130 drivers/staging/rtl8188eu/hal/phy.c 		phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
phy_set_bb_reg    104 drivers/staging/rtl8188eu/hal/rf.c 	phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
phy_set_bb_reg    106 drivers/staging/rtl8188eu/hal/rf.c 	phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
phy_set_bb_reg    110 drivers/staging/rtl8188eu/hal/rf.c 	phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
phy_set_bb_reg    112 drivers/staging/rtl8188eu/hal/rf.c 	phy_set_bb_reg(adapt, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
phy_set_bb_reg    255 drivers/staging/rtl8188eu/hal/rf.c 		phy_set_bb_reg(adapt, regoffset, bMaskDWord, write_val);
phy_set_bb_reg    231 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
phy_set_bb_reg    234 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
phy_set_bb_reg    237 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0);
phy_set_bb_reg    240 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0);
phy_set_bb_reg    245 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV, u4val);
phy_set_bb_reg    588 drivers/staging/rtl8188eu/hal/usb_halinit.c 	phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
phy_set_bb_reg    589 drivers/staging/rtl8188eu/hal/usb_halinit.c 	phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
phy_set_bb_reg    601 drivers/staging/rtl8188eu/hal/usb_halinit.c 	phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
phy_set_bb_reg     13 drivers/staging/rtl8188eu/include/phy.h void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data);