phm_phase_shedding_limits_table 1542 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			struct phm_phase_shedding_limits_table *table;
phm_phase_shedding_limits_table 1547 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(sizeof(struct phm_phase_shedding_limits_table) *
phm_phase_shedding_limits_table 2320 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					 struct phm_phase_shedding_limits_table *tab)
phm_phase_shedding_limits_table  635 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
phm_phase_shedding_limits_table  370 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				const struct phm_phase_shedding_limits_table *pl,
phm_phase_shedding_limits_table 1155 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
phm_phase_shedding_limits_table  874 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				const struct phm_phase_shedding_limits_table *pl,
phm_phase_shedding_limits_table 1210 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,