CRA 563 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_write(mac->adapter, CRA(4, port, i), 0); CRA 623 drivers/net/ethernet/chelsio/cxgb/vsc7326.c rmon_update(mac, CRA(0x4, port, p->reg), stats + p->offset); CRA 17 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */ CRA 18 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */ CRA 19 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */ CRA 20 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */ CRA 21 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */ CRA 22 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */ CRA 23 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */ CRA 24 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */ CRA 25 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */ CRA 26 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */ CRA 27 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */ CRA 28 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */ CRA 29 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */ CRA 30 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */ CRA 31 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */ CRA 32 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */ CRA 33 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */ CRA 36 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */ CRA 37 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */ CRA 38 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */ CRA 39 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */ CRA 40 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */ CRA 41 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */ CRA 42 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */ CRA 43 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */ CRA 44 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */ CRA 45 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */ CRA 46 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */ CRA 47 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */ CRA 52 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */ CRA 53 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */ CRA 71 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */ CRA 72 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */ CRA 73 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */ CRA 74 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */ CRA 75 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */ CRA 76 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */ CRA 77 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */ CRA 78 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */ CRA 79 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */ CRA 80 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */ CRA 87 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4)) CRA 88 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b) CRA 90 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */ CRA 91 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */ CRA 92 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */ CRA 93 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */ CRA 94 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */ CRA 95 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */ CRA 96 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */ CRA 97 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */ CRA 99 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */ CRA 100 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */ CRA 101 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */ CRA 102 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */ CRA 103 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */ CRA 104 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */ CRA 105 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */ CRA 108 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */ CRA 109 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */ CRA 110 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */ CRA 111 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */ CRA 112 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */ CRA 113 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */ CRA 114 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ CRA 115 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */ CRA 116 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */ CRA 117 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */ CRA 118 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */ CRA 119 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */ CRA 120 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */ CRA 121 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */ CRA 122 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */ CRA 123 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */ CRA 124 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */ CRA 125 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */ CRA 126 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */ CRA 127 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */ CRA 129 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */ CRA 141 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */ CRA 142 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */ CRA 143 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */ CRA 144 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */ CRA 145 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */ CRA 146 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */ CRA 147 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */ CRA 148 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */ CRA 149 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */ CRA 150 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */ CRA 151 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */ CRA 152 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */ CRA 153 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */ CRA 154 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */ CRA 155 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */ CRA 156 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */ CRA 157 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */ CRA 158 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */ CRA 159 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */ CRA 160 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */ CRA 161 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */ CRA 162 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */ CRA 163 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */ CRA 167 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */ CRA 168 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */ CRA 169 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */ CRA 174 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */ CRA 175 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */ CRA 176 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */ CRA 177 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */ CRA 178 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */ CRA 179 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */ CRA 180 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */ CRA 181 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */ CRA 182 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */ CRA 183 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */ CRA 184 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */ CRA 185 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */ CRA 186 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */ CRA 187 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */ CRA 188 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */ CRA 189 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */ CRA 190 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */ CRA 191 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */ CRA 192 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */ CRA 193 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */ CRA 268 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */ CRA 269 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */ CRA 271 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes) CRA 272 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes) CRA 273 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes) CRA 281 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */ CRA 282 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */ CRA 283 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */ CRA 284 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */ CRA 286 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd) CRA 287 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d) CRA 288 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d) CRA 289 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d) CRA 290 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d) CRA 291 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d) CRA 292 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d) CRA 293 drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h #define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d) CRA 1179 sound/soc/sh/fsi.c u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; CRA 1345 sound/soc/sh/fsi.c u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;