CR99              363 drivers/video/fbdev/via/dvi.c 			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
CR99              369 drivers/video/fbdev/via/dvi.c 			viafb_write_reg_mask(CR99, VIACR, 0x08,
CR99              376 drivers/video/fbdev/via/dvi.c 			viafb_write_reg_mask(CR99, VIACR, 0x0F,
CR99             2090 drivers/video/fbdev/via/hw.c 			viafb_write_reg_mask(CR99, VIACR,
CR99             2099 drivers/video/fbdev/via/hw.c 			viafb_write_reg_mask(CR99, VIACR,
CR99              519 drivers/video/fbdev/via/lcd.c 			viafb_write_reg_mask(CR99, VIACR, 0x08,
CR99             1288 drivers/video/fbdev/via/viafbdev.c 	dfp_low = viafb_read_reg(VIACR, CR99) & 0x0f;
CR99             1307 drivers/video/fbdev/via/viafbdev.c 	viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f);
CR99               38 drivers/video/fbdev/via/viamode.c {VIACR, CR99, 0xFF, 0x00},
CR99               87 drivers/video/fbdev/via/viamode.c {VIACR, CR99, 0xFF, 0x00},
CR99              126 drivers/video/fbdev/via/viamode.c 	{VIACR, CR99, 0xFF, 0x03},	/* DFP low           ; DFPL Clock Skew*/
CR99              162 drivers/video/fbdev/via/viamode.c {VIACR, CR99, 0xFF, 0x00},
CR99              193 drivers/video/fbdev/via/viamode.c {VIACR, CR99, 0xFF, 0x00},