pe                 57 arch/alpha/include/asm/core_marvel.h #define EV7_IPE(pe)		((~((long)(pe)) & EV7_PE_MASK) << 35)
pe                 59 arch/alpha/include/asm/core_marvel.h #define EV7_CSR_PHYS(pe, off)	(EV7_IPE(pe) | (0x7FFCUL << 20) | (off))
pe                 60 arch/alpha/include/asm/core_marvel.h #define EV7_CSRS_PHYS(pe)	(EV7_CSR_PHYS(pe, 0UL))
pe                 62 arch/alpha/include/asm/core_marvel.h #define EV7_CSR_KERN(pe, off)	(EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off)))
pe                 63 arch/alpha/include/asm/core_marvel.h #define EV7_CSRS_KERN(pe)	(EV7_KERN_ADDR(EV7_CSRS_PHYS(pe)))
pe                249 arch/alpha/include/asm/core_marvel.h #define IO7_IPE(pe)		(EV7_IPE(pe))
pe                252 arch/alpha/include/asm/core_marvel.h #define IO7_HOSE(pe, port)	(IO7_IPE(pe) | IO7_IPORT(port))
pe                254 arch/alpha/include/asm/core_marvel.h #define IO7_MEM_PHYS(pe, port)	(IO7_HOSE(pe, port) | 0x00000000UL)
pe                255 arch/alpha/include/asm/core_marvel.h #define IO7_CONF_PHYS(pe, port)	(IO7_HOSE(pe, port) | 0xFE000000UL)
pe                256 arch/alpha/include/asm/core_marvel.h #define IO7_IO_PHYS(pe, port)	(IO7_HOSE(pe, port) | 0xFF000000UL)
pe                257 arch/alpha/include/asm/core_marvel.h #define IO7_CSR_PHYS(pe, port, off) \
pe                258 arch/alpha/include/asm/core_marvel.h                                 (IO7_HOSE(pe, port) | 0xFF800000UL | (off))
pe                259 arch/alpha/include/asm/core_marvel.h #define IO7_CSRS_PHYS(pe, port)	(IO7_CSR_PHYS(pe, port, 0UL))
pe                260 arch/alpha/include/asm/core_marvel.h #define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))
pe                262 arch/alpha/include/asm/core_marvel.h #define IO7_MEM_KERN(pe, port)      (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port)))
pe                263 arch/alpha/include/asm/core_marvel.h #define IO7_CONF_KERN(pe, port)     (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port)))
pe                264 arch/alpha/include/asm/core_marvel.h #define IO7_IO_KERN(pe, port)       (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port)))
pe                265 arch/alpha/include/asm/core_marvel.h #define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off)))
pe                266 arch/alpha/include/asm/core_marvel.h #define IO7_CSRS_KERN(pe, port)     (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port)))
pe                267 arch/alpha/include/asm/core_marvel.h #define IO7_PORT7_CSRS_KERN(pe)	    (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe)))
pe                312 arch/alpha/include/asm/core_marvel.h 	unsigned int pe;
pe                 56 arch/alpha/kernel/core_marvel.c read_ev7_csr(int pe, unsigned long offset)
pe                 58 arch/alpha/kernel/core_marvel.c 	ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
pe                 69 arch/alpha/kernel/core_marvel.c write_ev7_csr(int pe, unsigned long offset, unsigned long q)
pe                 71 arch/alpha/kernel/core_marvel.c 	ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
pe                 79 arch/alpha/kernel/core_marvel.c mk_resource_name(int pe, int port, char *str)
pe                 84 arch/alpha/kernel/core_marvel.c 	sprintf(tmp, "PCI %s PE %d PORT %d", str, pe, port);
pe                101 arch/alpha/kernel/core_marvel.c marvel_find_io7(int pe)
pe                105 arch/alpha/kernel/core_marvel.c 	for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next)
pe                112 arch/alpha/kernel/core_marvel.c alloc_io7(unsigned int pe)
pe                118 arch/alpha/kernel/core_marvel.c 	if (marvel_find_io7(pe)) {
pe                119 arch/alpha/kernel/core_marvel.c 		printk(KERN_WARNING "IO7 at PE %d already allocated!\n", pe);
pe                127 arch/alpha/kernel/core_marvel.c 	io7->pe = pe;
pe                141 arch/alpha/kernel/core_marvel.c 	else if (io7_head->pe > io7->pe) {	/* insert at head */
pe                146 arch/alpha/kernel/core_marvel.c 			if (insp->pe == io7->pe) {
pe                148 arch/alpha/kernel/core_marvel.c 				       io7->pe);
pe                153 arch/alpha/kernel/core_marvel.c 			    insp->next->pe > io7->pe) { /* insert here */
pe                162 arch/alpha/kernel/core_marvel.c 			       " - adding at head of list\n", io7->pe);
pe                183 arch/alpha/kernel/core_marvel.c 		csrs = IO7_CSRS_KERN(io7->pe, port);
pe                194 arch/alpha/kernel/core_marvel.c 	p7csrs = IO7_PORT7_CSRS_KERN(io7->pe);
pe                212 arch/alpha/kernel/core_marvel.c 	io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port);
pe                240 arch/alpha/kernel/core_marvel.c 	hose->dense_mem_base = IO7_MEM_PHYS(io7->pe, port);
pe                241 arch/alpha/kernel/core_marvel.c 	hose->dense_io_base = IO7_IO_PHYS(io7->pe, port);
pe                246 arch/alpha/kernel/core_marvel.c 	hose->config_space_base = (unsigned long)IO7_CONF_KERN(io7->pe, port);
pe                248 arch/alpha/kernel/core_marvel.c 	hose->io_space->start = (unsigned long)IO7_IO_KERN(io7->pe, port);
pe                250 arch/alpha/kernel/core_marvel.c 	hose->io_space->name = mk_resource_name(io7->pe, port, "IO");
pe                253 arch/alpha/kernel/core_marvel.c 	hose->mem_space->start = (unsigned long)IO7_MEM_KERN(io7->pe, port);
pe                255 arch/alpha/kernel/core_marvel.c 	hose->mem_space->name = mk_resource_name(io7->pe, port, "MEM");
pe                291 arch/alpha/kernel/core_marvel.c 	hose->sg_isa = iommu_arena_new_node(marvel_cpuid_to_nid(io7->pe),
pe                309 arch/alpha/kernel/core_marvel.c 	hose->sg_pci = iommu_arena_new_node(marvel_cpuid_to_nid(io7->pe),
pe                342 arch/alpha/kernel/core_marvel.c 	printk("Initializing IO7 at PID %d\n", io7->pe);
pe                347 arch/alpha/kernel/core_marvel.c 	io7->csrs = IO7_PORT7_CSRS_KERN(io7->pe);
pe                353 arch/alpha/kernel/core_marvel.c 		io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, i);
pe                364 arch/alpha/kernel/core_marvel.c 	int pe;
pe                370 arch/alpha/kernel/core_marvel.c 	pe = (node->id >> 8) & 0xff;
pe                371 arch/alpha/kernel/core_marvel.c 	printk("Found an IO7 at PID %d\n", pe);
pe                373 arch/alpha/kernel/core_marvel.c 	alloc_io7(pe);
pe                897 arch/alpha/kernel/err_marvel.c 	lf_subpackets->io_pid = io7->pe;
pe                344 arch/alpha/kernel/perf_event.c 	struct perf_event *pe;
pe                354 arch/alpha/kernel/perf_event.c 	for_each_sibling_event(pe, group) {
pe                355 arch/alpha/kernel/perf_event.c 		if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) {
pe                358 arch/alpha/kernel/perf_event.c 			event[n] = pe;
pe                359 arch/alpha/kernel/perf_event.c 			evtype[n] = pe->hw.event_base;
pe                400 arch/alpha/kernel/perf_event.c 		struct perf_event *pe = cpuc->event[j];
pe                403 arch/alpha/kernel/perf_event.c 			cpuc->current_idx[j] != pe->hw.idx) {
pe                404 arch/alpha/kernel/perf_event.c 			alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0);
pe                412 arch/alpha/kernel/perf_event.c 		struct perf_event *pe = cpuc->event[j];
pe                413 arch/alpha/kernel/perf_event.c 		struct hw_perf_event *hwc = &pe->hw;
pe                417 arch/alpha/kernel/perf_event.c 			alpha_perf_event_set_period(pe, hwc, idx);
pe                 59 arch/alpha/kernel/proto.h struct io7 *marvel_find_io7(int pe);
pe                250 arch/alpha/kernel/sys_marvel.c 	long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
pe                254 arch/alpha/kernel/sys_marvel.c 		io7->pe, base);
pe                360 arch/alpha/kernel/sys_marvel.c 		       (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT),
pe                361 arch/alpha/kernel/sys_marvel.c 		       (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT));
pe                375 arch/alpha/kernel/sys_marvel.c 	irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT;	/* merge the pid     */
pe               3716 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pe:1;
pe               3722 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pe:1;
pe               4131 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pe:1;
pe               4137 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pe:1;
pe                106 arch/powerpc/include/asm/eeh.h #define eeh_pe_for_each_dev(pe, edev, tmp) \
pe                107 arch/powerpc/include/asm/eeh.h 		list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
pe                109 arch/powerpc/include/asm/eeh.h #define eeh_for_each_pe(root, pe) \
pe                110 arch/powerpc/include/asm/eeh.h 	for (pe = root; pe; pe = eeh_pe_next(pe, root))
pe                112 arch/powerpc/include/asm/eeh.h static inline bool eeh_pe_passed(struct eeh_pe *pe)
pe                114 arch/powerpc/include/asm/eeh.h 	return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
pe                145 arch/powerpc/include/asm/eeh.h 	struct eeh_pe *pe;		/* Associated PE		*/
pe                159 arch/powerpc/include/asm/eeh.h 	((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
pe                177 arch/powerpc/include/asm/eeh.h 	return edev ? edev->pe : NULL;
pe                219 arch/powerpc/include/asm/eeh.h 	int (*set_option)(struct eeh_pe *pe, int option);
pe                220 arch/powerpc/include/asm/eeh.h 	int (*get_pe_addr)(struct eeh_pe *pe);
pe                221 arch/powerpc/include/asm/eeh.h 	int (*get_state)(struct eeh_pe *pe, int *delay);
pe                222 arch/powerpc/include/asm/eeh.h 	int (*reset)(struct eeh_pe *pe, int option);
pe                223 arch/powerpc/include/asm/eeh.h 	int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
pe                224 arch/powerpc/include/asm/eeh.h 	int (*configure_bridge)(struct eeh_pe *pe);
pe                225 arch/powerpc/include/asm/eeh.h 	int (*err_inject)(struct eeh_pe *pe, int type, int func,
pe                229 arch/powerpc/include/asm/eeh.h 	int (*next_error)(struct eeh_pe **pe);
pe                277 arch/powerpc/include/asm/eeh.h typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
pe                280 arch/powerpc/include/asm/eeh.h int eeh_wait_state(struct eeh_pe *pe, int max_wait);
pe                282 arch/powerpc/include/asm/eeh.h struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
pe                287 arch/powerpc/include/asm/eeh.h void eeh_pe_update_time_stamp(struct eeh_pe *pe);
pe                292 arch/powerpc/include/asm/eeh.h void eeh_pe_restore_bars(struct eeh_pe *pe);
pe                293 arch/powerpc/include/asm/eeh.h const char *eeh_pe_loc_get(struct eeh_pe *pe);
pe                294 arch/powerpc/include/asm/eeh.h struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
pe                310 arch/powerpc/include/asm/eeh.h int eeh_unfreeze_pe(struct eeh_pe *pe);
pe                311 arch/powerpc/include/asm/eeh.h int eeh_pe_reset_and_recover(struct eeh_pe *pe);
pe                315 arch/powerpc/include/asm/eeh.h int eeh_pe_set_option(struct eeh_pe *pe, int option);
pe                316 arch/powerpc/include/asm/eeh.h int eeh_pe_get_state(struct eeh_pe *pe);
pe                317 arch/powerpc/include/asm/eeh.h int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
pe                318 arch/powerpc/include/asm/eeh.h int eeh_pe_configure(struct eeh_pe *pe);
pe                319 arch/powerpc/include/asm/eeh.h int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
pe                 19 arch/powerpc/include/asm/eeh_event.h 	struct eeh_pe		*pe;	/* EEH PE		*/
pe                 23 arch/powerpc/include/asm/eeh_event.h int eeh_send_failure_event(struct eeh_pe *pe);
pe                 24 arch/powerpc/include/asm/eeh_event.h int __eeh_send_failure_event(struct eeh_pe *pe);
pe                 25 arch/powerpc/include/asm/eeh_event.h void eeh_remove_event(struct eeh_pe *pe, bool force);
pe                 26 arch/powerpc/include/asm/eeh_event.h void eeh_handle_normal_event(struct eeh_pe *pe);
pe                 50 arch/powerpc/include/asm/ppc-pci.h void eeh_slot_error_detail(struct eeh_pe *pe, int severity);
pe                 51 arch/powerpc/include/asm/ppc-pci.h int eeh_pci_enable(struct eeh_pe *pe, int function);
pe                 52 arch/powerpc/include/asm/ppc-pci.h int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed);
pe                 56 arch/powerpc/include/asm/ppc-pci.h void eeh_pe_state_mark(struct eeh_pe *pe, int state);
pe                 57 arch/powerpc/include/asm/ppc-pci.h void eeh_pe_mark_isolated(struct eeh_pe *pe);
pe                 58 arch/powerpc/include/asm/ppc-pci.h void eeh_pe_state_clear(struct eeh_pe *pe, int state, bool include_passed);
pe                 59 arch/powerpc/include/asm/ppc-pci.h void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state);
pe                 60 arch/powerpc/include/asm/ppc-pci.h void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);
pe                275 arch/powerpc/kernel/eeh.c static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
pe                280 arch/powerpc/kernel/eeh.c 	eeh_pe_for_each_dev(pe, edev, tmp)
pe                297 arch/powerpc/kernel/eeh.c void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
pe                317 arch/powerpc/kernel/eeh.c 	if (!(pe->type & EEH_PE_PHB)) {
pe                320 arch/powerpc/kernel/eeh.c 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
pe                334 arch/powerpc/kernel/eeh.c 		eeh_ops->configure_bridge(pe);
pe                335 arch/powerpc/kernel/eeh.c 		if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
pe                336 arch/powerpc/kernel/eeh.c 			eeh_pe_restore_bars(pe);
pe                339 arch/powerpc/kernel/eeh.c 			eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
pe                343 arch/powerpc/kernel/eeh.c 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
pe                387 arch/powerpc/kernel/eeh.c static int eeh_phb_check_failure(struct eeh_pe *pe)
pe                397 arch/powerpc/kernel/eeh.c 	phb_pe = eeh_phb_pe_get(pe->phb);
pe                400 arch/powerpc/kernel/eeh.c 			__func__, pe->phb->global_number);
pe                452 arch/powerpc/kernel/eeh.c 	struct eeh_pe *pe, *parent_pe;
pe                466 arch/powerpc/kernel/eeh.c 	pe = eeh_dev_to_pe(edev);
pe                469 arch/powerpc/kernel/eeh.c 	if (!pe) {
pe                475 arch/powerpc/kernel/eeh.c 	if (!pe->addr && !pe->config_addr) {
pe                484 arch/powerpc/kernel/eeh.c 	ret = eeh_phb_check_failure(pe);
pe                493 arch/powerpc/kernel/eeh.c 	if (eeh_pe_passed(pe))
pe                504 arch/powerpc/kernel/eeh.c 	if (pe->state & EEH_PE_ISOLATED) {
pe                505 arch/powerpc/kernel/eeh.c 		pe->check_count++;
pe                506 arch/powerpc/kernel/eeh.c 		if (pe->check_count % EEH_MAX_FAILS == 0) {
pe                512 arch/powerpc/kernel/eeh.c 				pe->check_count,
pe                529 arch/powerpc/kernel/eeh.c 	ret = eeh_ops->get_state(pe, NULL);
pe                540 arch/powerpc/kernel/eeh.c 		pe->false_positives++;
pe                550 arch/powerpc/kernel/eeh.c 	parent_pe = pe->parent;
pe                559 arch/powerpc/kernel/eeh.c 			pe = parent_pe;
pe                561 arch/powerpc/kernel/eeh.c 			       pe->phb->global_number, pe->addr,
pe                562 arch/powerpc/kernel/eeh.c 			       pe->phb->global_number, parent_pe->addr);
pe                575 arch/powerpc/kernel/eeh.c 	eeh_pe_mark_isolated(pe);
pe                583 arch/powerpc/kernel/eeh.c 		__func__, pe->phb->global_number, pe->addr);
pe                584 arch/powerpc/kernel/eeh.c 	eeh_send_failure_event(pe);
pe                632 arch/powerpc/kernel/eeh.c int eeh_pci_enable(struct eeh_pe *pe, int function)
pe                664 arch/powerpc/kernel/eeh.c 		rc = eeh_ops->get_state(pe, NULL);
pe                679 arch/powerpc/kernel/eeh.c 	rc = eeh_ops->set_option(pe, function);
pe                683 arch/powerpc/kernel/eeh.c 			__func__, function, pe->phb->global_number,
pe                684 arch/powerpc/kernel/eeh.c 			pe->addr, rc);
pe                688 arch/powerpc/kernel/eeh.c 		rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
pe                815 arch/powerpc/kernel/eeh.c 	struct eeh_pe *pe = eeh_dev_to_pe(edev);
pe                817 arch/powerpc/kernel/eeh.c 	if (!pe) {
pe                825 arch/powerpc/kernel/eeh.c 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
pe                826 arch/powerpc/kernel/eeh.c 		eeh_unfreeze_pe(pe);
pe                827 arch/powerpc/kernel/eeh.c 		if (!(pe->type & EEH_PE_VF))
pe                828 arch/powerpc/kernel/eeh.c 			eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
pe                829 arch/powerpc/kernel/eeh.c 		eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
pe                830 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
pe                833 arch/powerpc/kernel/eeh.c 		eeh_pe_mark_isolated(pe);
pe                834 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
pe                835 arch/powerpc/kernel/eeh.c 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
pe                836 arch/powerpc/kernel/eeh.c 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
pe                837 arch/powerpc/kernel/eeh.c 		if (!(pe->type & EEH_PE_VF))
pe                838 arch/powerpc/kernel/eeh.c 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
pe                839 arch/powerpc/kernel/eeh.c 		eeh_ops->reset(pe, EEH_RESET_HOT);
pe                842 arch/powerpc/kernel/eeh.c 		eeh_pe_mark_isolated(pe);
pe                843 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
pe                844 arch/powerpc/kernel/eeh.c 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
pe                845 arch/powerpc/kernel/eeh.c 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
pe                846 arch/powerpc/kernel/eeh.c 		if (!(pe->type & EEH_PE_VF))
pe                847 arch/powerpc/kernel/eeh.c 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
pe                848 arch/powerpc/kernel/eeh.c 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
pe                851 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);
pe                880 arch/powerpc/kernel/eeh.c 	struct eeh_pe *pe;
pe                883 arch/powerpc/kernel/eeh.c 	eeh_for_each_pe(root, pe) {
pe                884 arch/powerpc/kernel/eeh.c 		if (eeh_pe_passed(pe)) {
pe                885 arch/powerpc/kernel/eeh.c 			state = eeh_ops->get_state(pe, NULL);
pe                889 arch/powerpc/kernel/eeh.c 					pe->phb->global_number, pe->addr);
pe                890 arch/powerpc/kernel/eeh.c 				eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
pe                908 arch/powerpc/kernel/eeh.c int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)
pe                920 arch/powerpc/kernel/eeh.c 	eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
pe                926 arch/powerpc/kernel/eeh.c 	eeh_pe_state_mark(pe, reset_state);
pe                930 arch/powerpc/kernel/eeh.c 		ret = eeh_pe_reset(pe, type, include_passed);
pe                932 arch/powerpc/kernel/eeh.c 			ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,
pe                937 arch/powerpc/kernel/eeh.c 				state, pe->phb->global_number, pe->addr, i + 1);
pe                942 arch/powerpc/kernel/eeh.c 				pe->phb->global_number, pe->addr, i + 1);
pe                945 arch/powerpc/kernel/eeh.c 		state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
pe                948 arch/powerpc/kernel/eeh.c 				pe->phb->global_number, pe->addr);
pe                956 arch/powerpc/kernel/eeh.c 				pe->phb->global_number, pe->addr, state, i + 1);
pe                963 arch/powerpc/kernel/eeh.c 		eeh_pe_refreeze_passed(pe);
pe                965 arch/powerpc/kernel/eeh.c 	eeh_pe_state_clear(pe, reset_state, true);
pe               1285 arch/powerpc/kernel/eeh.c 	if (!edev || !edev->pdev || !edev->pe) {
pe               1306 arch/powerpc/kernel/eeh.c 	if (!(edev->pe->state & EEH_PE_KEEP))
pe               1324 arch/powerpc/kernel/eeh.c int eeh_unfreeze_pe(struct eeh_pe *pe)
pe               1328 arch/powerpc/kernel/eeh.c 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
pe               1331 arch/powerpc/kernel/eeh.c 			__func__, ret, pe->phb->global_number, pe->addr);
pe               1335 arch/powerpc/kernel/eeh.c 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
pe               1338 arch/powerpc/kernel/eeh.c 			__func__, ret, pe->phb->global_number, pe->addr);
pe               1353 arch/powerpc/kernel/eeh.c static int eeh_pe_change_owner(struct eeh_pe *pe)
pe               1361 arch/powerpc/kernel/eeh.c 	ret = eeh_ops->get_state(pe, NULL);
pe               1370 arch/powerpc/kernel/eeh.c 	eeh_pe_for_each_dev(pe, edev, tmp) {
pe               1389 arch/powerpc/kernel/eeh.c 			return eeh_pe_reset_and_recover(pe);
pe               1393 arch/powerpc/kernel/eeh.c 	ret = eeh_unfreeze_pe(pe);
pe               1395 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
pe               1421 arch/powerpc/kernel/eeh.c 	if (!edev || !edev->pe)
pe               1430 arch/powerpc/kernel/eeh.c 	ret = eeh_pe_change_owner(edev->pe);
pe               1435 arch/powerpc/kernel/eeh.c 	atomic_inc(&edev->pe->pass_dev_cnt);
pe               1465 arch/powerpc/kernel/eeh.c 	if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
pe               1469 arch/powerpc/kernel/eeh.c 	WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
pe               1470 arch/powerpc/kernel/eeh.c 	eeh_pe_change_owner(edev->pe);
pe               1516 arch/powerpc/kernel/eeh.c 	if (!edev || !edev->pe)
pe               1519 arch/powerpc/kernel/eeh.c 	return edev->pe;
pe               1533 arch/powerpc/kernel/eeh.c int eeh_pe_set_option(struct eeh_pe *pe, int option)
pe               1538 arch/powerpc/kernel/eeh.c 	if (!pe)
pe               1549 arch/powerpc/kernel/eeh.c 			ret = eeh_pe_change_owner(pe);
pe               1564 arch/powerpc/kernel/eeh.c 		ret = eeh_pci_enable(pe, option);
pe               1583 arch/powerpc/kernel/eeh.c int eeh_pe_get_state(struct eeh_pe *pe)
pe               1589 arch/powerpc/kernel/eeh.c 	if (!pe)
pe               1601 arch/powerpc/kernel/eeh.c 	if (pe->parent &&
pe               1602 arch/powerpc/kernel/eeh.c 	    !(pe->state & EEH_PE_REMOVED) &&
pe               1603 arch/powerpc/kernel/eeh.c 	    (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
pe               1606 arch/powerpc/kernel/eeh.c 	result = eeh_ops->get_state(pe, NULL);
pe               1626 arch/powerpc/kernel/eeh.c static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)
pe               1632 arch/powerpc/kernel/eeh.c 	eeh_pe_restore_bars(pe);
pe               1638 arch/powerpc/kernel/eeh.c 	eeh_pe_for_each_dev(pe, edev, tmp) {
pe               1652 arch/powerpc/kernel/eeh.c 	if (include_passed || !eeh_pe_passed(pe)) {
pe               1653 arch/powerpc/kernel/eeh.c 		ret = eeh_unfreeze_pe(pe);
pe               1656 arch/powerpc/kernel/eeh.c 			pe->phb->global_number, pe->addr);
pe               1658 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);
pe               1672 arch/powerpc/kernel/eeh.c int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)
pe               1677 arch/powerpc/kernel/eeh.c 	if (!pe)
pe               1685 arch/powerpc/kernel/eeh.c 		ret = eeh_ops->reset(pe, option);
pe               1686 arch/powerpc/kernel/eeh.c 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);
pe               1690 arch/powerpc/kernel/eeh.c 		ret = eeh_pe_reenable_devices(pe, include_passed);
pe               1699 arch/powerpc/kernel/eeh.c 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
pe               1701 arch/powerpc/kernel/eeh.c 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
pe               1702 arch/powerpc/kernel/eeh.c 		ret = eeh_ops->reset(pe, option);
pe               1722 arch/powerpc/kernel/eeh.c int eeh_pe_configure(struct eeh_pe *pe)
pe               1727 arch/powerpc/kernel/eeh.c 	if (!pe)
pe               1746 arch/powerpc/kernel/eeh.c int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
pe               1750 arch/powerpc/kernel/eeh.c 	if (!pe)
pe               1765 arch/powerpc/kernel/eeh.c 	return eeh_ops->err_inject(pe, type, func, addr, mask);
pe               1825 arch/powerpc/kernel/eeh.c 	struct eeh_pe *pe;
pe               1853 arch/powerpc/kernel/eeh.c 	pe = eeh_pe_get(hose, pe_no, 0);
pe               1854 arch/powerpc/kernel/eeh.c 	if (!pe)
pe               1864 arch/powerpc/kernel/eeh.c 	__eeh_send_failure_event(pe);
pe                181 arch/powerpc/kernel/eeh_cache.c 	if (!edev->pe) {
pe                106 arch/powerpc/kernel/eeh_driver.c 	if (eeh_pe_passed(edev->pe))
pe                223 arch/powerpc/kernel/eeh_driver.c 	if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED))
pe                235 arch/powerpc/kernel/eeh_driver.c 	struct eeh_pe *pe;
pe                238 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(root, pe)
pe                239 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_for_each_dev(pe, edev, tmp)
pe                246 arch/powerpc/kernel/eeh_driver.c 	struct eeh_pe *pe;
pe                249 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(root, pe) {
pe                250 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_for_each_dev(pe, edev, tmp) {
pe                309 arch/powerpc/kernel/eeh_driver.c 			      !eeh_dev_removed(edev), !eeh_pe_passed(edev->pe));
pe                324 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(root, pe) eeh_pe_for_each_dev(pe, edev, tmp)
pe                409 arch/powerpc/kernel/eeh_driver.c 	if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED)) {
pe                410 arch/powerpc/kernel/eeh_driver.c 		if (list_is_last(&edev->entry, &edev->pe->edevs))
pe                581 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(root, pe) {
pe                582 arch/powerpc/kernel/eeh_driver.c 		if (include_passed || !eeh_pe_passed(pe)) {
pe                584 arch/powerpc/kernel/eeh_driver.c 				if (!eeh_unfreeze_pe(pe))
pe                594 arch/powerpc/kernel/eeh_driver.c int eeh_pe_reset_and_recover(struct eeh_pe *pe)
pe                599 arch/powerpc/kernel/eeh_driver.c 	if (pe->state & EEH_PE_RECOVERING)
pe                603 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
pe                606 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_dev_traverse(pe, eeh_dev_save_state, NULL);
pe                609 arch/powerpc/kernel/eeh_driver.c 	ret = eeh_pe_reset_full(pe, true);
pe                611 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);
pe                616 arch/powerpc/kernel/eeh_driver.c 	ret = eeh_clear_pe_frozen_state(pe, true);
pe                618 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);
pe                623 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_dev_traverse(pe, eeh_dev_restore_state, NULL);
pe                626 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);
pe                642 arch/powerpc/kernel/eeh_driver.c static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus,
pe                652 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(pe, tmp_pe)
pe                656 arch/powerpc/kernel/eeh_driver.c 	cnt = pe->freeze_count;
pe                657 arch/powerpc/kernel/eeh_driver.c 	tstamp = pe->tstamp;
pe                665 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_state_mark(pe, EEH_PE_KEEP);
pe                666 arch/powerpc/kernel/eeh_driver.c 	if (any_passed || driver_eeh_aware || (pe->type & EEH_PE_VF)) {
pe                667 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_dev_traverse(pe, eeh_rmv_device, rmv_data);
pe                683 arch/powerpc/kernel/eeh_driver.c 	rc = eeh_pe_reset_full(pe, false);
pe                690 arch/powerpc/kernel/eeh_driver.c 	eeh_ops->configure_bridge(pe);
pe                691 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_restore_bars(pe);
pe                694 arch/powerpc/kernel/eeh_driver.c 	rc = eeh_clear_pe_frozen_state(pe, false);
pe                716 arch/powerpc/kernel/eeh_driver.c 		edev = list_first_entry(&pe->edevs, struct eeh_dev, entry);
pe                717 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_traverse(pe, eeh_pe_detach_dev, NULL);
pe                718 arch/powerpc/kernel/eeh_driver.c 		if (pe->type & EEH_PE_VF) {
pe                722 arch/powerpc/kernel/eeh_driver.c 				eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);
pe                726 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_state_clear(pe, EEH_PE_KEEP, true);
pe                728 arch/powerpc/kernel/eeh_driver.c 	pe->tstamp = tstamp;
pe                729 arch/powerpc/kernel/eeh_driver.c 	pe->freeze_count = cnt;
pe                748 arch/powerpc/kernel/eeh_driver.c static void eeh_pe_cleanup(struct eeh_pe *pe)
pe                752 arch/powerpc/kernel/eeh_driver.c 	list_for_each_entry_safe(child_pe, tmp, &pe->child_list, child)
pe                755 arch/powerpc/kernel/eeh_driver.c 	if (pe->state & EEH_PE_KEEP)
pe                758 arch/powerpc/kernel/eeh_driver.c 	if (!(pe->state & EEH_PE_INVALID))
pe                761 arch/powerpc/kernel/eeh_driver.c 	if (list_empty(&pe->edevs) && list_empty(&pe->child_list)) {
pe                762 arch/powerpc/kernel/eeh_driver.c 		list_del(&pe->child);
pe                763 arch/powerpc/kernel/eeh_driver.c 		kfree(pe);
pe                854 arch/powerpc/kernel/eeh_driver.c void eeh_handle_normal_event(struct eeh_pe *pe)
pe                865 arch/powerpc/kernel/eeh_driver.c 	bus = eeh_pe_bus_get(pe);
pe                868 arch/powerpc/kernel/eeh_driver.c 			__func__, pe->phb->global_number, pe->addr);
pe                881 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(pe, tmp_pe)
pe                888 arch/powerpc/kernel/eeh_driver.c 			pe->phb->global_number, pe->addr);
pe                893 arch/powerpc/kernel/eeh_driver.c 	if (pe->type & EEH_PE_PHB) {
pe                895 arch/powerpc/kernel/eeh_driver.c 			pe->phb->global_number, eeh_pe_loc_get(pe));
pe                897 arch/powerpc/kernel/eeh_driver.c 		struct eeh_pe *phb_pe = eeh_phb_pe_get(pe->phb);
pe                900 arch/powerpc/kernel/eeh_driver.c 		       pe->phb->global_number, pe->addr);
pe                902 arch/powerpc/kernel/eeh_driver.c 		       eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
pe                910 arch/powerpc/kernel/eeh_driver.c 	if (pe->trace_entries) {
pe                911 arch/powerpc/kernel/eeh_driver.c 		void **ptrs = (void **) pe->stack_trace;
pe                915 arch/powerpc/kernel/eeh_driver.c 		       pe->phb->global_number, pe->addr);
pe                919 arch/powerpc/kernel/eeh_driver.c 		for (i = 0; i < pe->trace_entries; i++)
pe                922 arch/powerpc/kernel/eeh_driver.c 		pe->trace_entries = 0;
pe                926 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_update_time_stamp(pe);
pe                927 arch/powerpc/kernel/eeh_driver.c 	pe->freeze_count++;
pe                928 arch/powerpc/kernel/eeh_driver.c 	if (pe->freeze_count > eeh_max_freezes) {
pe                930 arch/powerpc/kernel/eeh_driver.c 		       pe->phb->global_number, pe->addr,
pe                931 arch/powerpc/kernel/eeh_driver.c 		       pe->freeze_count);
pe                935 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(pe, tmp_pe)
pe                951 arch/powerpc/kernel/eeh_driver.c 			pe->freeze_count, eeh_max_freezes);
pe                953 arch/powerpc/kernel/eeh_driver.c 		eeh_set_channel_state(pe, pci_channel_io_frozen);
pe                954 arch/powerpc/kernel/eeh_driver.c 		eeh_set_irq_state(pe, false);
pe                955 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_report("error_detected(IO frozen)", pe,
pe                957 arch/powerpc/kernel/eeh_driver.c 		if ((pe->type & EEH_PE_PHB) &&
pe                967 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_wait_state(pe, MAX_WAIT_FOR_RECOVERY*1000);
pe                980 arch/powerpc/kernel/eeh_driver.c 		eeh_slot_error_detail(pe, EEH_LOG_TEMP);
pe                989 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_reset_device(pe, bus, NULL, false);
pe               1000 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
pe               1008 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_report("mmio_enabled", pe,
pe               1016 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
pe               1028 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
pe               1036 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_reset_device(pe, bus, &rmv_data, true);
pe               1043 arch/powerpc/kernel/eeh_driver.c 			eeh_set_channel_state(pe, pci_channel_io_normal);
pe               1044 arch/powerpc/kernel/eeh_driver.c 			eeh_set_irq_state(pe, true);
pe               1045 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_report("slot_reset", pe, eeh_report_reset,
pe               1064 arch/powerpc/kernel/eeh_driver.c 		eeh_set_channel_state(pe, pci_channel_io_normal);
pe               1065 arch/powerpc/kernel/eeh_driver.c 		eeh_set_irq_state(pe, true);
pe               1066 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_report("resume", pe, eeh_report_resume, NULL);
pe               1067 arch/powerpc/kernel/eeh_driver.c 		eeh_for_each_pe(pe, tmp_pe) {
pe               1083 arch/powerpc/kernel/eeh_driver.c 			pe->phb->global_number, pe->addr);
pe               1085 arch/powerpc/kernel/eeh_driver.c 		eeh_slot_error_detail(pe, EEH_LOG_PERM);
pe               1088 arch/powerpc/kernel/eeh_driver.c 		eeh_set_channel_state(pe, pci_channel_io_perm_failure);
pe               1089 arch/powerpc/kernel/eeh_driver.c 		eeh_set_irq_state(pe, false);
pe               1090 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_report("error_detected(permanent failure)", pe,
pe               1094 arch/powerpc/kernel/eeh_driver.c 		eeh_pe_state_mark(pe, EEH_PE_REMOVED);
pe               1101 arch/powerpc/kernel/eeh_driver.c 		if (pe->type & EEH_PE_VF) {
pe               1102 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_dev_traverse(pe, eeh_rmv_device, NULL);
pe               1103 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_dev_mode_mark(pe, EEH_DEV_REMOVED);
pe               1105 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);
pe               1106 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_dev_mode_mark(pe, EEH_DEV_REMOVED);
pe               1121 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_cleanup(pe);
pe               1124 arch/powerpc/kernel/eeh_driver.c 	eeh_for_each_pe(pe, tmp_pe)
pe               1128 arch/powerpc/kernel/eeh_driver.c 	eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);
pe               1140 arch/powerpc/kernel/eeh_driver.c 	struct eeh_pe *pe, *phb_pe, *tmp_pe;
pe               1149 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_ops->next_error(&pe);
pe               1176 arch/powerpc/kernel/eeh_driver.c 			eeh_remove_event(pe, true);
pe               1179 arch/powerpc/kernel/eeh_driver.c 				eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
pe               1180 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_mark_isolated(pe);
pe               1200 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
pe               1201 arch/powerpc/kernel/eeh_driver.c 			eeh_handle_normal_event(pe);
pe               1203 arch/powerpc/kernel/eeh_driver.c 			eeh_for_each_pe(pe, tmp_pe)
pe               1208 arch/powerpc/kernel/eeh_driver.c 			eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);
pe               1209 arch/powerpc/kernel/eeh_driver.c 			eeh_set_channel_state(pe, pci_channel_io_perm_failure);
pe               1211 arch/powerpc/kernel/eeh_driver.c 				"error_detected(permanent failure)", pe,
pe               1227 arch/powerpc/kernel/eeh_driver.c 					       pe->phb->global_number,
pe               1228 arch/powerpc/kernel/eeh_driver.c 					       pe->addr);
pe                 61 arch/powerpc/kernel/eeh_event.c 		if (event->pe)
pe                 62 arch/powerpc/kernel/eeh_event.c 			eeh_handle_normal_event(event->pe);
pe                102 arch/powerpc/kernel/eeh_event.c int __eeh_send_failure_event(struct eeh_pe *pe)
pe                112 arch/powerpc/kernel/eeh_event.c 	event->pe = pe;
pe                119 arch/powerpc/kernel/eeh_event.c 	if (pe) {
pe                125 arch/powerpc/kernel/eeh_event.c 		pe->trace_entries = stack_trace_save(pe->stack_trace,
pe                126 arch/powerpc/kernel/eeh_event.c 					 ARRAY_SIZE(pe->stack_trace), 0);
pe                129 arch/powerpc/kernel/eeh_event.c 		eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
pe                143 arch/powerpc/kernel/eeh_event.c int eeh_send_failure_event(struct eeh_pe *pe)
pe                154 arch/powerpc/kernel/eeh_event.c 	return __eeh_send_failure_event(pe);
pe                167 arch/powerpc/kernel/eeh_event.c void eeh_remove_event(struct eeh_pe *pe, bool force)
pe                183 arch/powerpc/kernel/eeh_event.c 		if (!force && event->pe &&
pe                184 arch/powerpc/kernel/eeh_event.c 		    (event->pe->state & EEH_PE_ISOLATED))
pe                187 arch/powerpc/kernel/eeh_event.c 		if (!pe) {
pe                190 arch/powerpc/kernel/eeh_event.c 		} else if (pe->type & EEH_PE_PHB) {
pe                191 arch/powerpc/kernel/eeh_event.c 			if (event->pe && event->pe->phb == pe->phb) {
pe                195 arch/powerpc/kernel/eeh_event.c 		} else if (event->pe == pe) {
pe                 48 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                 58 arch/powerpc/kernel/eeh_pe.c 	pe = kzalloc(alloc_size, GFP_KERNEL);
pe                 59 arch/powerpc/kernel/eeh_pe.c 	if (!pe) return NULL;
pe                 62 arch/powerpc/kernel/eeh_pe.c 	pe->type = type;
pe                 63 arch/powerpc/kernel/eeh_pe.c 	pe->phb = phb;
pe                 64 arch/powerpc/kernel/eeh_pe.c 	INIT_LIST_HEAD(&pe->child_list);
pe                 65 arch/powerpc/kernel/eeh_pe.c 	INIT_LIST_HEAD(&pe->edevs);
pe                 67 arch/powerpc/kernel/eeh_pe.c 	pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
pe                 69 arch/powerpc/kernel/eeh_pe.c 	return pe;
pe                 81 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                 84 arch/powerpc/kernel/eeh_pe.c 	pe = eeh_pe_alloc(phb, EEH_PE_PHB);
pe                 85 arch/powerpc/kernel/eeh_pe.c 	if (!pe) {
pe                 91 arch/powerpc/kernel/eeh_pe.c 	list_add_tail(&pe->child, &eeh_phb_pe);
pe                106 arch/powerpc/kernel/eeh_pe.c int eeh_wait_state(struct eeh_pe *pe, int max_wait)
pe                123 arch/powerpc/kernel/eeh_pe.c 		ret = eeh_ops->get_state(pe, &mwait);
pe                159 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                161 arch/powerpc/kernel/eeh_pe.c 	list_for_each_entry(pe, &eeh_phb_pe, child) {
pe                167 arch/powerpc/kernel/eeh_pe.c 		if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
pe                168 arch/powerpc/kernel/eeh_pe.c 			return pe;
pe                182 arch/powerpc/kernel/eeh_pe.c struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)
pe                184 arch/powerpc/kernel/eeh_pe.c 	struct list_head *next = pe->child_list.next;
pe                186 arch/powerpc/kernel/eeh_pe.c 	if (next == &pe->child_list) {
pe                188 arch/powerpc/kernel/eeh_pe.c 			if (pe == root)
pe                190 arch/powerpc/kernel/eeh_pe.c 			next = pe->child.next;
pe                191 arch/powerpc/kernel/eeh_pe.c 			if (next != &pe->parent->child_list)
pe                193 arch/powerpc/kernel/eeh_pe.c 			pe = pe->parent;
pe                214 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                217 arch/powerpc/kernel/eeh_pe.c 	eeh_for_each_pe(root, pe) {
pe                218 arch/powerpc/kernel/eeh_pe.c 		ret = fn(pe, flag);
pe                237 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                247 arch/powerpc/kernel/eeh_pe.c 	eeh_for_each_pe(root, pe)
pe                248 arch/powerpc/kernel/eeh_pe.c 		eeh_pe_for_each_dev(pe, edev, tmp)
pe                267 arch/powerpc/kernel/eeh_pe.c static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)
pe                272 arch/powerpc/kernel/eeh_pe.c 	if (pe->type & EEH_PE_PHB)
pe                280 arch/powerpc/kernel/eeh_pe.c 		if (tmp->pe_no == pe->addr)
pe                281 arch/powerpc/kernel/eeh_pe.c 			return pe;
pe                284 arch/powerpc/kernel/eeh_pe.c 		    (tmp->pe_no == pe->addr))
pe                285 arch/powerpc/kernel/eeh_pe.c 			return pe;
pe                290 arch/powerpc/kernel/eeh_pe.c 	   (tmp->config_addr == pe->config_addr))
pe                291 arch/powerpc/kernel/eeh_pe.c 		return pe;
pe                314 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                316 arch/powerpc/kernel/eeh_pe.c 	pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
pe                318 arch/powerpc/kernel/eeh_pe.c 	return pe;
pe                349 arch/powerpc/kernel/eeh_pe.c 		if (parent->pe)
pe                350 arch/powerpc/kernel/eeh_pe.c 			return parent->pe;
pe                369 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe, *parent;
pe                385 arch/powerpc/kernel/eeh_pe.c 	pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr);
pe                386 arch/powerpc/kernel/eeh_pe.c 	if (pe) {
pe                387 arch/powerpc/kernel/eeh_pe.c 		if (pe->type & EEH_PE_INVALID) {
pe                388 arch/powerpc/kernel/eeh_pe.c 			list_add_tail(&edev->entry, &pe->edevs);
pe                389 arch/powerpc/kernel/eeh_pe.c 			edev->pe = pe;
pe                394 arch/powerpc/kernel/eeh_pe.c 			parent = pe;
pe                404 arch/powerpc/kernel/eeh_pe.c 				     pe->parent->addr);
pe                407 arch/powerpc/kernel/eeh_pe.c 			pe->type = EEH_PE_BUS;
pe                408 arch/powerpc/kernel/eeh_pe.c 			edev->pe = pe;
pe                411 arch/powerpc/kernel/eeh_pe.c 			list_add_tail(&edev->entry, &pe->edevs);
pe                419 arch/powerpc/kernel/eeh_pe.c 		pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF);
pe                421 arch/powerpc/kernel/eeh_pe.c 		pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE);
pe                422 arch/powerpc/kernel/eeh_pe.c 	if (!pe) {
pe                426 arch/powerpc/kernel/eeh_pe.c 	pe->addr	= edev->pe_config_addr;
pe                427 arch/powerpc/kernel/eeh_pe.c 	pe->config_addr	= config_addr;
pe                441 arch/powerpc/kernel/eeh_pe.c 			edev->pe = NULL;
pe                442 arch/powerpc/kernel/eeh_pe.c 			kfree(pe);
pe                446 arch/powerpc/kernel/eeh_pe.c 	pe->parent = parent;
pe                452 arch/powerpc/kernel/eeh_pe.c 	list_add_tail(&pe->child, &parent->child_list);
pe                453 arch/powerpc/kernel/eeh_pe.c 	list_add_tail(&edev->entry, &pe->edevs);
pe                454 arch/powerpc/kernel/eeh_pe.c 	edev->pe = pe;
pe                456 arch/powerpc/kernel/eeh_pe.c 		     pe->parent->addr);
pe                472 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe, *parent, *child;
pe                476 arch/powerpc/kernel/eeh_pe.c 	pe = eeh_dev_to_pe(edev);
pe                477 arch/powerpc/kernel/eeh_pe.c 	if (!pe) {
pe                483 arch/powerpc/kernel/eeh_pe.c 	edev->pe = NULL;
pe                493 arch/powerpc/kernel/eeh_pe.c 		parent = pe->parent;
pe                496 arch/powerpc/kernel/eeh_pe.c 		if (pe->type & EEH_PE_PHB)
pe                504 arch/powerpc/kernel/eeh_pe.c 		keep = !!(pe->state & EEH_PE_KEEP);
pe                505 arch/powerpc/kernel/eeh_pe.c 		recover = !!(pe->state & EEH_PE_RECOVERING);
pe                509 arch/powerpc/kernel/eeh_pe.c 			if (list_empty(&pe->edevs) &&
pe                510 arch/powerpc/kernel/eeh_pe.c 			    list_empty(&pe->child_list)) {
pe                511 arch/powerpc/kernel/eeh_pe.c 				list_del(&pe->child);
pe                512 arch/powerpc/kernel/eeh_pe.c 				kfree(pe);
pe                526 arch/powerpc/kernel/eeh_pe.c 			if (list_empty(&pe->edevs)) {
pe                528 arch/powerpc/kernel/eeh_pe.c 				list_for_each_entry(child, &pe->child_list, child) {
pe                536 arch/powerpc/kernel/eeh_pe.c 					pe->type |= EEH_PE_INVALID;
pe                542 arch/powerpc/kernel/eeh_pe.c 		pe = parent;
pe                557 arch/powerpc/kernel/eeh_pe.c void eeh_pe_update_time_stamp(struct eeh_pe *pe)
pe                561 arch/powerpc/kernel/eeh_pe.c 	if (!pe) return;
pe                563 arch/powerpc/kernel/eeh_pe.c 	if (pe->freeze_count <= 0) {
pe                564 arch/powerpc/kernel/eeh_pe.c 		pe->freeze_count = 0;
pe                565 arch/powerpc/kernel/eeh_pe.c 		pe->tstamp = ktime_get_seconds();
pe                568 arch/powerpc/kernel/eeh_pe.c 		if (tstamp - pe->tstamp > 3600) {
pe                569 arch/powerpc/kernel/eeh_pe.c 			pe->tstamp = tstamp;
pe                570 arch/powerpc/kernel/eeh_pe.c 			pe->freeze_count = 0;
pe                585 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                587 arch/powerpc/kernel/eeh_pe.c 	eeh_for_each_pe(root, pe)
pe                588 arch/powerpc/kernel/eeh_pe.c 		if (!(pe->state & EEH_PE_REMOVED))
pe                589 arch/powerpc/kernel/eeh_pe.c 			pe->state |= state;
pe                603 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                608 arch/powerpc/kernel/eeh_pe.c 	eeh_for_each_pe(root, pe) {
pe                609 arch/powerpc/kernel/eeh_pe.c 		list_for_each_entry(edev, &pe->edevs, entry) {
pe                615 arch/powerpc/kernel/eeh_pe.c 		if (pe->state & EEH_PE_CFG_RESTRICTED)
pe                616 arch/powerpc/kernel/eeh_pe.c 			pe->state |= EEH_PE_CFG_BLOCKED;
pe                634 arch/powerpc/kernel/eeh_pe.c void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
pe                636 arch/powerpc/kernel/eeh_pe.c 	eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
pe                651 arch/powerpc/kernel/eeh_pe.c 	struct eeh_pe *pe;
pe                655 arch/powerpc/kernel/eeh_pe.c 	eeh_for_each_pe(root, pe) {
pe                657 arch/powerpc/kernel/eeh_pe.c 		if (pe->state & EEH_PE_REMOVED)
pe                660 arch/powerpc/kernel/eeh_pe.c 		if (!include_passed && eeh_pe_passed(pe))
pe                663 arch/powerpc/kernel/eeh_pe.c 		pe->state &= ~state;
pe                673 arch/powerpc/kernel/eeh_pe.c 		pe->check_count = 0;
pe                674 arch/powerpc/kernel/eeh_pe.c 		eeh_pe_for_each_dev(pe, edev, tmp) {
pe                683 arch/powerpc/kernel/eeh_pe.c 		if (pe->state & EEH_PE_CFG_RESTRICTED)
pe                684 arch/powerpc/kernel/eeh_pe.c 			pe->state &= ~EEH_PE_CFG_BLOCKED;
pe                865 arch/powerpc/kernel/eeh_pe.c void eeh_pe_restore_bars(struct eeh_pe *pe)
pe                871 arch/powerpc/kernel/eeh_pe.c 	eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
pe                883 arch/powerpc/kernel/eeh_pe.c const char *eeh_pe_loc_get(struct eeh_pe *pe)
pe                885 arch/powerpc/kernel/eeh_pe.c 	struct pci_bus *bus = eeh_pe_bus_get(pe);
pe                921 arch/powerpc/kernel/eeh_pe.c struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
pe                926 arch/powerpc/kernel/eeh_pe.c 	if (pe->type & EEH_PE_PHB)
pe                927 arch/powerpc/kernel/eeh_pe.c 		return pe->phb->bus;
pe                930 arch/powerpc/kernel/eeh_pe.c 	if (pe->state & EEH_PE_PRI_BUS)
pe                931 arch/powerpc/kernel/eeh_pe.c 		return pe->bus;
pe                934 arch/powerpc/kernel/eeh_pe.c 	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
pe                 63 arch/powerpc/kernel/eeh_sysfs.c 	if (!edev || !edev->pe)
pe                 66 arch/powerpc/kernel/eeh_sysfs.c 	state = eeh_ops->get_state(edev->pe, NULL);
pe                 68 arch/powerpc/kernel/eeh_sysfs.c 		       state, edev->pe->state);
pe                 78 arch/powerpc/kernel/eeh_sysfs.c 	if (!edev || !edev->pe)
pe                 82 arch/powerpc/kernel/eeh_sysfs.c 	if (!(edev->pe->state & EEH_PE_ISOLATED))
pe                 85 arch/powerpc/kernel/eeh_sysfs.c 	if (eeh_unfreeze_pe(edev->pe))
pe                 87 arch/powerpc/kernel/eeh_sysfs.c 	eeh_pe_state_clear(edev->pe, EEH_PE_ISOLATED, true);
pe                102 arch/powerpc/kernel/eeh_sysfs.c 	if (!edev || !edev->pe)
pe                116 arch/powerpc/kernel/eeh_sysfs.c 	if (!edev || !edev->pe || !eeh_ops->notify_resume)
pe                260 arch/powerpc/kernel/pci_dn.c 				if (edev->pe)
pe                 56 arch/powerpc/kernel/rtas_pci.c 	if (pdn->edev && pdn->edev->pe &&
pe                 57 arch/powerpc/kernel/rtas_pci.c 	    (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
pe                107 arch/powerpc/kernel/rtas_pci.c 	if (pdn->edev && pdn->edev->pe &&
pe                108 arch/powerpc/kernel/rtas_pci.c 	    (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
pe                124 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct eeh_pe *pe;
pe                145 arch/powerpc/platforms/powernv/eeh-powernv.c 	pe = eeh_pe_get(hose, pe_no, 0);
pe                146 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (!pe)
pe                150 arch/powerpc/platforms/powernv/eeh-powernv.c 	ret = eeh_ops->err_inject(pe, type, func, addr, mask);
pe                380 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (!edev || edev->pe)
pe                444 arch/powerpc/platforms/powernv/eeh-powernv.c 		edev->pe->state |= EEH_PE_CFG_RESTRICTED;
pe                452 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
pe                453 arch/powerpc/platforms/powernv/eeh-powernv.c 		edev->pe->bus = pci_find_bus(hose->global_number,
pe                455 arch/powerpc/platforms/powernv/eeh-powernv.c 		if (edev->pe->bus)
pe                456 arch/powerpc/platforms/powernv/eeh-powernv.c 			edev->pe->state |= EEH_PE_PRI_BUS;
pe                486 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
pe                488 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct pci_controller *hose = pe->phb;
pe                517 arch/powerpc/platforms/powernv/eeh-powernv.c 			phb->freeze_pe(phb, pe->addr);
pe                521 arch/powerpc/platforms/powernv/eeh-powernv.c 		rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
pe                525 arch/powerpc/platforms/powernv/eeh-powernv.c 				pe->addr);
pe                534 arch/powerpc/platforms/powernv/eeh-powernv.c 		return phb->unfreeze_pe(phb, pe->addr, opt);
pe                536 arch/powerpc/platforms/powernv/eeh-powernv.c 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
pe                540 arch/powerpc/platforms/powernv/eeh-powernv.c 			pe->addr);
pe                554 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
pe                556 arch/powerpc/platforms/powernv/eeh-powernv.c 	return pe->addr;
pe                559 arch/powerpc/platforms/powernv/eeh-powernv.c static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
pe                561 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct pnv_phb *phb = pe->phb->private_data;
pe                564 arch/powerpc/platforms/powernv/eeh-powernv.c 	rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
pe                568 arch/powerpc/platforms/powernv/eeh-powernv.c 			__func__, rc, pe->phb->global_number);
pe                571 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
pe                573 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct pnv_phb *phb = pe->phb->private_data;
pe                580 arch/powerpc/platforms/powernv/eeh-powernv.c 					pe->addr,
pe                599 arch/powerpc/platforms/powernv/eeh-powernv.c 	} else if (!(pe->state & EEH_PE_ISOLATED)) {
pe                600 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_pe_mark_isolated(pe);
pe                601 arch/powerpc/platforms/powernv/eeh-powernv.c 		pnv_eeh_get_phb_diag(pe);
pe                604 arch/powerpc/platforms/powernv/eeh-powernv.c 			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
pe                610 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
pe                612 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct pnv_phb *phb = pe->phb->private_data;
pe                624 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (pe->state & EEH_PE_RESET) {
pe                637 arch/powerpc/platforms/powernv/eeh-powernv.c 		fstate = phb->get_pe_state(phb, pe->addr);
pe                640 arch/powerpc/platforms/powernv/eeh-powernv.c 						pe->addr,
pe                647 arch/powerpc/platforms/powernv/eeh-powernv.c 				pe->addr);
pe                684 arch/powerpc/platforms/powernv/eeh-powernv.c 			pe->addr, fstate);
pe                698 arch/powerpc/platforms/powernv/eeh-powernv.c 	    !(pe->state & EEH_PE_ISOLATED)) {
pe                700 arch/powerpc/platforms/powernv/eeh-powernv.c 			phb->freeze_pe(phb, pe->addr);
pe                702 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_pe_mark_isolated(pe);
pe                703 arch/powerpc/platforms/powernv/eeh-powernv.c 		pnv_eeh_get_phb_diag(pe);
pe                706 arch/powerpc/platforms/powernv/eeh-powernv.c 			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
pe                722 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
pe                726 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (pe->type & EEH_PE_PHB)
pe                727 arch/powerpc/platforms/powernv/eeh-powernv.c 		ret = pnv_eeh_get_phb_state(pe);
pe                729 arch/powerpc/platforms/powernv/eeh-powernv.c 		ret = pnv_eeh_get_pe_state(pe);
pe               1047 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
pe               1054 arch/powerpc/platforms/powernv/eeh-powernv.c 	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
pe               1078 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_reset(struct eeh_pe *pe, int option)
pe               1080 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct pci_controller *hose = pe->phb;
pe               1099 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (pe->type & EEH_PE_PHB)
pe               1123 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (pe->type & EEH_PE_VF)
pe               1124 arch/powerpc/platforms/powernv/eeh-powernv.c 		return pnv_eeh_reset_vf_pe(pe, option);
pe               1126 arch/powerpc/platforms/powernv/eeh-powernv.c 	bus = eeh_pe_bus_get(pe);
pe               1129 arch/powerpc/platforms/powernv/eeh-powernv.c 			__func__, pe->phb->global_number, pe->addr);
pe               1176 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
pe               1180 arch/powerpc/platforms/powernv/eeh-powernv.c 		pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
pe               1193 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
pe               1210 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
pe               1213 arch/powerpc/platforms/powernv/eeh-powernv.c 	struct pci_controller *hose = pe->phb;
pe               1239 arch/powerpc/platforms/powernv/eeh-powernv.c 	rc = opal_pci_err_inject(phb->opal_id, pe->addr,
pe               1245 arch/powerpc/platforms/powernv/eeh-powernv.c 			hose->global_number, pe->addr);
pe               1256 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (!edev || !edev->pe)
pe               1264 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
pe               1267 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (edev->pe->state & EEH_PE_CFG_BLOCKED)
pe               1381 arch/powerpc/platforms/powernv/eeh-powernv.c 			  u16 pe_no, struct eeh_pe **pe)
pe               1406 arch/powerpc/platforms/powernv/eeh-powernv.c 	*pe = dev_pe;
pe               1425 arch/powerpc/platforms/powernv/eeh-powernv.c 		*pe = dev_pe;
pe               1446 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_next_error(struct eeh_pe **pe)
pe               1514 arch/powerpc/platforms/powernv/eeh-powernv.c 				*pe = phb_pe;
pe               1522 arch/powerpc/platforms/powernv/eeh-powernv.c 				*pe = phb_pe;
pe               1545 arch/powerpc/platforms/powernv/eeh-powernv.c 				be64_to_cpu(frozen_pe_no), pe)) {
pe               1563 arch/powerpc/platforms/powernv/eeh-powernv.c 			} else if ((*pe)->state & EEH_PE_ISOLATED ||
pe               1564 arch/powerpc/platforms/powernv/eeh-powernv.c 				   eeh_pe_passed(*pe)) {
pe               1569 arch/powerpc/platforms/powernv/eeh-powernv.c 				       (*pe)->addr,
pe               1570 arch/powerpc/platforms/powernv/eeh-powernv.c 					(*pe)->phb->global_number);
pe               1573 arch/powerpc/platforms/powernv/eeh-powernv.c 				       eeh_pe_loc_get(*pe),
pe               1593 arch/powerpc/platforms/powernv/eeh-powernv.c 		    !((*pe)->state & EEH_PE_ISOLATED)) {
pe               1594 arch/powerpc/platforms/powernv/eeh-powernv.c 			eeh_pe_mark_isolated(*pe);
pe               1595 arch/powerpc/platforms/powernv/eeh-powernv.c 			pnv_eeh_get_phb_diag(*pe);
pe               1598 arch/powerpc/platforms/powernv/eeh-powernv.c 				pnv_pci_dump_phb_diag_data((*pe)->phb,
pe               1599 arch/powerpc/platforms/powernv/eeh-powernv.c 							   (*pe)->data);
pe               1607 arch/powerpc/platforms/powernv/eeh-powernv.c 			parent_pe = (*pe)->parent;
pe               1616 arch/powerpc/platforms/powernv/eeh-powernv.c 					*pe = parent_pe;
pe               1623 arch/powerpc/platforms/powernv/eeh-powernv.c 			eeh_pe_mark_isolated(*pe);
pe                103 arch/powerpc/platforms/powernv/npu-dma.c 	struct pnv_ioda_pe *pe;
pe                116 arch/powerpc/platforms/powernv/npu-dma.c 	pe = &phb->ioda.pe_array[pdn->pe_number];
pe                121 arch/powerpc/platforms/powernv/npu-dma.c 	return pe;
pe                264 arch/powerpc/platforms/powernv/npu-dma.c 	struct pnv_ioda_pe *pe[NV_NPU_MAX_PE_NUM];
pe                282 arch/powerpc/platforms/powernv/npu-dma.c 	if (!npucomp->pe_num || !npucomp->pe[0] ||
pe                283 arch/powerpc/platforms/powernv/npu-dma.c 			!npucomp->pe[0]->table_group.ops ||
pe                284 arch/powerpc/platforms/powernv/npu-dma.c 			!npucomp->pe[0]->table_group.ops->create_table)
pe                287 arch/powerpc/platforms/powernv/npu-dma.c 	return npucomp->pe[0]->table_group.ops->create_table(
pe                288 arch/powerpc/platforms/powernv/npu-dma.c 			&npucomp->pe[0]->table_group, num, page_shift,
pe                301 arch/powerpc/platforms/powernv/npu-dma.c 		struct pnv_ioda_pe *pe = npucomp->pe[i];
pe                303 arch/powerpc/platforms/powernv/npu-dma.c 		if (!pe->table_group.ops->set_window)
pe                306 arch/powerpc/platforms/powernv/npu-dma.c 		ret = pe->table_group.ops->set_window(&pe->table_group,
pe                314 arch/powerpc/platforms/powernv/npu-dma.c 			struct pnv_ioda_pe *pe = npucomp->pe[j];
pe                316 arch/powerpc/platforms/powernv/npu-dma.c 			if (!pe->table_group.ops->unset_window)
pe                319 arch/powerpc/platforms/powernv/npu-dma.c 			ret = pe->table_group.ops->unset_window(
pe                320 arch/powerpc/platforms/powernv/npu-dma.c 					&pe->table_group, num);
pe                340 arch/powerpc/platforms/powernv/npu-dma.c 		struct pnv_ioda_pe *pe = npucomp->pe[i];
pe                347 arch/powerpc/platforms/powernv/npu-dma.c 		if (!pe->table_group.ops->unset_window)
pe                350 arch/powerpc/platforms/powernv/npu-dma.c 		ret = pe->table_group.ops->unset_window(&pe->table_group, num);
pe                357 arch/powerpc/platforms/powernv/npu-dma.c 			struct pnv_ioda_pe *pe = npucomp->pe[j];
pe                362 arch/powerpc/platforms/powernv/npu-dma.c 			if (!pe->table_group.ops->set_window)
pe                365 arch/powerpc/platforms/powernv/npu-dma.c 			ret = pe->table_group.ops->set_window(&pe->table_group,
pe                385 arch/powerpc/platforms/powernv/npu-dma.c 		struct pnv_ioda_pe *pe = npucomp->pe[i];
pe                387 arch/powerpc/platforms/powernv/npu-dma.c 		if (!pe->table_group.ops->take_ownership)
pe                389 arch/powerpc/platforms/powernv/npu-dma.c 		pe->table_group.ops->take_ownership(&pe->table_group);
pe                401 arch/powerpc/platforms/powernv/npu-dma.c 		struct pnv_ioda_pe *pe = npucomp->pe[i];
pe                403 arch/powerpc/platforms/powernv/npu-dma.c 		if (!pe->table_group.ops->release_ownership)
pe                405 arch/powerpc/platforms/powernv/npu-dma.c 		pe->table_group.ops->release_ownership(&pe->table_group);
pe                419 arch/powerpc/platforms/powernv/npu-dma.c 		struct pnv_ioda_pe *pe)
pe                424 arch/powerpc/platforms/powernv/npu-dma.c 	npucomp->pe[npucomp->pe_num] = pe;
pe                428 arch/powerpc/platforms/powernv/npu-dma.c struct iommu_table_group *pnv_try_setup_npu_table_group(struct pnv_ioda_pe *pe)
pe                436 arch/powerpc/platforms/powernv/npu-dma.c 	list_for_each_entry(gpdev, &pe->pbus->devices, bus_list) {
pe                455 arch/powerpc/platforms/powernv/npu-dma.c 					pe->pe_number);
pe                459 arch/powerpc/platforms/powernv/npu-dma.c 		pe->npucomp = kzalloc(sizeof(*pe->npucomp), GFP_KERNEL);
pe                460 arch/powerpc/platforms/powernv/npu-dma.c 		table_group = &pe->npucomp->table_group;
pe                463 arch/powerpc/platforms/powernv/npu-dma.c 				pe->pe_number);
pe                468 arch/powerpc/platforms/powernv/npu-dma.c 		pe->table_group.max_dynamic_windows_supported;
pe                469 arch/powerpc/platforms/powernv/npu-dma.c 	table_group->tce32_start = pe->table_group.tce32_start;
pe                470 arch/powerpc/platforms/powernv/npu-dma.c 	table_group->tce32_size = pe->table_group.tce32_size;
pe                471 arch/powerpc/platforms/powernv/npu-dma.c 	table_group->max_levels = pe->table_group.max_levels;
pe                473 arch/powerpc/platforms/powernv/npu-dma.c 		table_group->pgsizes = pe->table_group.pgsizes;
pe                476 arch/powerpc/platforms/powernv/npu-dma.c 	pnv_comp_attach_table_group(npucomp, pe);
pe                481 arch/powerpc/platforms/powernv/npu-dma.c struct iommu_table_group *pnv_npu_compound_attach(struct pnv_ioda_pe *pe)
pe                487 arch/powerpc/platforms/powernv/npu-dma.c 	struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(pe, &gpdev);
pe                489 arch/powerpc/platforms/powernv/npu-dma.c 	WARN_ON(!(pe->flags & PNV_IODA_PE_DEV));
pe                499 arch/powerpc/platforms/powernv/npu-dma.c 	pe->table_group.ops = &pnv_pci_npu_ops;
pe                509 arch/powerpc/platforms/powernv/npu-dma.c 	table_group->pgsizes &= pe->table_group.pgsizes;
pe                511 arch/powerpc/platforms/powernv/npu-dma.c 	pnv_comp_attach_table_group(npucomp, pe);
pe                513 arch/powerpc/platforms/powernv/npu-dma.c 	list_for_each_entry(npdev, &pe->phb->hose->bus->devices, bus_list) {
pe                 16 arch/powerpc/platforms/powernv/pci-cxl.c 	struct pnv_ioda_pe *pe;
pe                 19 arch/powerpc/platforms/powernv/pci-cxl.c 	pe = pnv_ioda_get_pe(dev);
pe                 20 arch/powerpc/platforms/powernv/pci-cxl.c 	if (!pe)
pe                 23 arch/powerpc/platforms/powernv/pci-cxl.c 	pe_info(pe, "Switching PHB to CXL\n");
pe                 25 arch/powerpc/platforms/powernv/pci-cxl.c 	rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
pe                134 arch/powerpc/platforms/powernv/pci-cxl.c 	struct pnv_ioda_pe *pe;
pe                137 arch/powerpc/platforms/powernv/pci-cxl.c 	if (!(pe = pnv_ioda_get_pe(dev)))
pe                141 arch/powerpc/platforms/powernv/pci-cxl.c 	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
pe                143 arch/powerpc/platforms/powernv/pci-cxl.c 		pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
pe                 53 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
pe                 55 arch/powerpc/platforms/powernv/pci-ioda.c void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
pe                 67 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_DEV)
pe                 68 arch/powerpc/platforms/powernv/pci-ioda.c 		strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
pe                 69 arch/powerpc/platforms/powernv/pci-ioda.c 	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
pe                 71 arch/powerpc/platforms/powernv/pci-ioda.c 			pci_domain_nr(pe->pbus), pe->pbus->number);
pe                 73 arch/powerpc/platforms/powernv/pci-ioda.c 	else if (pe->flags & PNV_IODA_PE_VF)
pe                 75 arch/powerpc/platforms/powernv/pci-ioda.c 			pci_domain_nr(pe->parent_dev->bus),
pe                 76 arch/powerpc/platforms/powernv/pci-ioda.c 			(pe->rid & 0xff00) >> 8,
pe                 77 arch/powerpc/platforms/powernv/pci-ioda.c 			PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
pe                 81 arch/powerpc/platforms/powernv/pci-ioda.c 	       level, pfix, pe->pe_number, &vaf);
pe                175 arch/powerpc/platforms/powernv/pci-ioda.c 	long pe;
pe                177 arch/powerpc/platforms/powernv/pci-ioda.c 	for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
pe                178 arch/powerpc/platforms/powernv/pci-ioda.c 		if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
pe                179 arch/powerpc/platforms/powernv/pci-ioda.c 			return pnv_ioda_init_pe(phb, pe);
pe                185 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
pe                187 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe                188 arch/powerpc/platforms/powernv/pci-ioda.c 	unsigned int pe_num = pe->pe_number;
pe                190 arch/powerpc/platforms/powernv/pci-ioda.c 	WARN_ON(pe->pdev);
pe                191 arch/powerpc/platforms/powernv/pci-ioda.c 	WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
pe                192 arch/powerpc/platforms/powernv/pci-ioda.c 	kfree(pe->npucomp);
pe                193 arch/powerpc/platforms/powernv/pci-ioda.c 	memset(pe, 0, sizeof(struct pnv_ioda_pe));
pe                355 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *master_pe, *pe;
pe                393 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = &phb->ioda.pe_array[i];
pe                395 arch/powerpc/platforms/powernv/pci-ioda.c 		phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
pe                397 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->flags |= PNV_IODA_PE_MASTER;
pe                398 arch/powerpc/platforms/powernv/pci-ioda.c 			INIT_LIST_HEAD(&pe->slaves);
pe                399 arch/powerpc/platforms/powernv/pci-ioda.c 			master_pe = pe;
pe                401 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->flags |= PNV_IODA_PE_SLAVE;
pe                402 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->master = master_pe;
pe                403 arch/powerpc/platforms/powernv/pci-ioda.c 			list_add_tail(&pe->list, &master_pe->slaves);
pe                417 arch/powerpc/platforms/powernv/pci-ioda.c 					pe->pe_number, OPAL_M64_WINDOW_TYPE,
pe                418 arch/powerpc/platforms/powernv/pci-ioda.c 					pe->pe_number / PNV_IODA1_M64_SEGS,
pe                419 arch/powerpc/platforms/powernv/pci-ioda.c 					pe->pe_number % PNV_IODA1_M64_SEGS);
pe                423 arch/powerpc/platforms/powernv/pci-ioda.c 					pe->pe_number);
pe                523 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
pe                528 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_SLAVE) {
pe                529 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = pe->master;
pe                530 arch/powerpc/platforms/powernv/pci-ioda.c 		if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
pe                533 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_no = pe->pe_number;
pe                547 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!(pe->flags & PNV_IODA_PE_MASTER))
pe                550 arch/powerpc/platforms/powernv/pci-ioda.c 	list_for_each_entry(slave, &pe->slaves, list) {
pe                563 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe, *slave;
pe                567 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = &phb->ioda.pe_array[pe_no];
pe                568 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_SLAVE) {
pe                569 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = pe->master;
pe                570 arch/powerpc/platforms/powernv/pci-ioda.c 		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
pe                571 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_no = pe->pe_number;
pe                582 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!(pe->flags & PNV_IODA_PE_MASTER))
pe                586 arch/powerpc/platforms/powernv/pci-ioda.c 	list_for_each_entry(slave, &pe->slaves, list) {
pe                603 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *slave, *pe;
pe                616 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = &phb->ioda.pe_array[pe_no];
pe                617 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_SLAVE) {
pe                618 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = pe->master;
pe                619 arch/powerpc/platforms/powernv/pci-ioda.c 		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
pe                620 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_no = pe->pe_number;
pe                635 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!(pe->flags & PNV_IODA_PE_MASTER))
pe                638 arch/powerpc/platforms/powernv/pci-ioda.c 	list_for_each_entry(slave, &pe->slaves, list) {
pe                714 arch/powerpc/platforms/powernv/pci-ioda.c 			      struct pnv_ioda_pe *pe,
pe                726 arch/powerpc/platforms/powernv/pci-ioda.c 		opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
pe                728 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe->flags & PNV_IODA_PE_MASTER) {
pe                729 arch/powerpc/platforms/powernv/pci-ioda.c 			list_for_each_entry(slave, &pe->slaves, list)
pe                742 arch/powerpc/platforms/powernv/pci-ioda.c 	ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
pe                747 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_MASTER) {
pe                748 arch/powerpc/platforms/powernv/pci-ioda.c 		list_for_each_entry(slave, &pe->slaves, list) {
pe                749 arch/powerpc/platforms/powernv/pci-ioda.c 			ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
pe                755 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
pe                756 arch/powerpc/platforms/powernv/pci-ioda.c 		pdev = pe->pbus->self;
pe                757 arch/powerpc/platforms/powernv/pci-ioda.c 	else if (pe->flags & PNV_IODA_PE_DEV)
pe                758 arch/powerpc/platforms/powernv/pci-ioda.c 		pdev = pe->pdev->bus->self;
pe                760 arch/powerpc/platforms/powernv/pci-ioda.c 	else if (pe->flags & PNV_IODA_PE_VF)
pe                761 arch/powerpc/platforms/powernv/pci-ioda.c 		pdev = pe->parent_dev;
pe                769 arch/powerpc/platforms/powernv/pci-ioda.c 			ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
pe                780 arch/powerpc/platforms/powernv/pci-ioda.c static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
pe                788 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->pbus) {
pe                793 arch/powerpc/platforms/powernv/pci-ioda.c 		parent = pe->pbus->self;
pe                794 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe->flags & PNV_IODA_PE_BUS_ALL)
pe                795 arch/powerpc/platforms/powernv/pci-ioda.c 			count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
pe                807 arch/powerpc/platforms/powernv/pci-ioda.c 			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
pe                812 arch/powerpc/platforms/powernv/pci-ioda.c 		rid_end = pe->rid + (count << 8);
pe                815 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe->flags & PNV_IODA_PE_VF)
pe                816 arch/powerpc/platforms/powernv/pci-ioda.c 			parent = pe->parent_dev;
pe                819 arch/powerpc/platforms/powernv/pci-ioda.c 			parent = pe->pdev->bus->self;
pe                823 arch/powerpc/platforms/powernv/pci-ioda.c 		rid_end = pe->rid + 1;
pe                827 arch/powerpc/platforms/powernv/pci-ioda.c 	for (rid = pe->rid; rid < rid_end; rid++)
pe                835 arch/powerpc/platforms/powernv/pci-ioda.c 						pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
pe                841 arch/powerpc/platforms/powernv/pci-ioda.c 	opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
pe                845 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
pe                846 arch/powerpc/platforms/powernv/pci-ioda.c 				pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
pe                848 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
pe                849 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
pe                852 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
pe                854 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->pbus = NULL;
pe                855 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->pdev = NULL;
pe                857 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->parent_dev = NULL;
pe                863 arch/powerpc/platforms/powernv/pci-ioda.c static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
pe                870 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->pbus) {
pe                875 arch/powerpc/platforms/powernv/pci-ioda.c 		parent = pe->pbus->self;
pe                876 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe->flags & PNV_IODA_PE_BUS_ALL)
pe                877 arch/powerpc/platforms/powernv/pci-ioda.c 			count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
pe                889 arch/powerpc/platforms/powernv/pci-ioda.c 			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
pe                894 arch/powerpc/platforms/powernv/pci-ioda.c 		rid_end = pe->rid + (count << 8);
pe                897 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe->flags & PNV_IODA_PE_VF)
pe                898 arch/powerpc/platforms/powernv/pci-ioda.c 			parent = pe->parent_dev;
pe                901 arch/powerpc/platforms/powernv/pci-ioda.c 			parent = pe->pdev->bus->self;
pe                905 arch/powerpc/platforms/powernv/pci-ioda.c 		rid_end = pe->rid + 1;
pe                914 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
pe                917 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
pe                926 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_set_peltv(phb, pe, true);
pe                929 arch/powerpc/platforms/powernv/pci-ioda.c 	for (rid = pe->rid; rid < rid_end; rid++)
pe                930 arch/powerpc/platforms/powernv/pci-ioda.c 		phb->ioda.pe_rmap[rid] = pe->pe_number;
pe                934 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->mve_number = 0;
pe                938 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->mve_number = pe->pe_number;
pe                939 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
pe                941 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "OPAL error %ld setting up MVE %x\n",
pe                942 arch/powerpc/platforms/powernv/pci-ioda.c 		       rc, pe->mve_number);
pe                943 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->mve_number = -1;
pe                946 arch/powerpc/platforms/powernv/pci-ioda.c 					     pe->mve_number, OPAL_ENABLE_MVE);
pe                948 arch/powerpc/platforms/powernv/pci-ioda.c 			pe_err(pe, "OPAL error %ld enabling MVE %x\n",
pe                949 arch/powerpc/platforms/powernv/pci-ioda.c 			       rc, pe->mve_number);
pe                950 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->mve_number = -1;
pe               1048 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               1058 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = pnv_ioda_alloc_pe(phb);
pe               1059 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!pe) {
pe               1073 arch/powerpc/platforms/powernv/pci-ioda.c 	pdn->pe_number = pe->pe_number;
pe               1074 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->flags = PNV_IODA_PE_DEV;
pe               1075 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->pdev = dev;
pe               1076 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->pbus = NULL;
pe               1077 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->mve_number = -1;
pe               1078 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->rid = dev->bus->number << 8 | pdn->devfn;
pe               1080 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "Associated device to PE\n");
pe               1082 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pnv_ioda_configure_pe(phb, pe)) {
pe               1084 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe(pe);
pe               1086 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->pdev = NULL;
pe               1092 arch/powerpc/platforms/powernv/pci-ioda.c 	list_add_tail(&pe->list, &phb->ioda.pe_list);
pe               1094 arch/powerpc/platforms/powernv/pci-ioda.c 	return pe;
pe               1097 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
pe               1118 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->device_count++;
pe               1119 arch/powerpc/platforms/powernv/pci-ioda.c 		pdn->pe_number = pe->pe_number;
pe               1120 arch/powerpc/platforms/powernv/pci-ioda.c 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
pe               1121 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_setup_same_PE(dev->subordinate, pe);
pe               1135 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = NULL;
pe               1144 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = &phb->ioda.pe_array[pe_num];
pe               1145 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_same_PE(bus, pe);
pe               1152 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
pe               1155 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!pe)
pe               1156 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = pnv_ioda_pick_m64_pe(bus, all);
pe               1159 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!pe)
pe               1160 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = pnv_ioda_alloc_pe(phb);
pe               1162 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!pe) {
pe               1168 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
pe               1169 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->pbus = bus;
pe               1170 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->pdev = NULL;
pe               1171 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->mve_number = -1;
pe               1172 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->rid = bus->busn_res.start << 8;
pe               1175 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
pe               1177 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->pe_number);
pe               1179 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
pe               1180 arch/powerpc/platforms/powernv/pci-ioda.c 			&bus->busn_res.start, pe->pe_number);
pe               1182 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pnv_ioda_configure_pe(phb, pe)) {
pe               1184 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe(pe);
pe               1185 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->pbus = NULL;
pe               1190 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_ioda_setup_same_PE(bus, pe);
pe               1193 arch/powerpc/platforms/powernv/pci-ioda.c 	list_add_tail(&pe->list, &phb->ioda.pe_list);
pe               1195 arch/powerpc/platforms/powernv/pci-ioda.c 	return pe;
pe               1202 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               1219 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = &phb->ioda.pe_array[pe_num];
pe               1220 arch/powerpc/platforms/powernv/pci-ioda.c 		if (!pe->pdev)
pe               1223 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
pe               1235 arch/powerpc/platforms/powernv/pci-ioda.c 			phb->ioda.pe_rmap[rid] = pe->pe_number;
pe               1256 arch/powerpc/platforms/powernv/pci-ioda.c 		return pe;
pe               1273 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               1295 arch/powerpc/platforms/powernv/pci-ioda.c 		list_for_each_entry(pe, &phb->ioda.pe_list, list)
pe               1296 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
pe               1442 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
pe               1447 arch/powerpc/platforms/powernv/pci-ioda.c 	tbl = pe->table_group.tables[0];
pe               1448 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
pe               1450 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
pe               1452 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_ioda2_set_bypass(pe, false);
pe               1453 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->table_group.group) {
pe               1454 arch/powerpc/platforms/powernv/pci-ioda.c 		iommu_group_put(pe->table_group.group);
pe               1455 arch/powerpc/platforms/powernv/pci-ioda.c 		BUG_ON(pe->table_group.group);
pe               1465 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe    *pe, *pe_n;
pe               1476 arch/powerpc/platforms/powernv/pci-ioda.c 	list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
pe               1477 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe->parent_dev != pdev)
pe               1480 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda2_release_dma_pe(pdev, pe);
pe               1484 arch/powerpc/platforms/powernv/pci-ioda.c 		list_del(&pe->list);
pe               1487 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_deconfigure_pe(phb, pe);
pe               1489 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe(pe);
pe               1498 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe    *pe;
pe               1524 arch/powerpc/platforms/powernv/pci-ioda.c 				pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
pe               1525 arch/powerpc/platforms/powernv/pci-ioda.c 				pnv_ioda_free_pe(pe);
pe               1535 arch/powerpc/platforms/powernv/pci-ioda.c 				       struct pnv_ioda_pe *pe);
pe               1537 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
pe               1546 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe    *pe;
pe               1570 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = &phb->ioda.pe_array[pe_num];
pe               1571 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->pe_number = pe_num;
pe               1572 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->phb = phb;
pe               1573 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->flags = PNV_IODA_PE_VF;
pe               1574 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->pbus = NULL;
pe               1575 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->parent_dev = pdev;
pe               1576 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->mve_number = -1;
pe               1577 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->rid = (vf_bus << 8) | vf_devfn;
pe               1579 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
pe               1583 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pnv_ioda_configure_pe(phb, pe)) {
pe               1585 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_free_pe(pe);
pe               1586 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->pdev = NULL;
pe               1592 arch/powerpc/platforms/powernv/pci-ioda.c 		list_add_tail(&pe->list, &phb->ioda.pe_list);
pe               1604 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda2_setup_dma_pe(phb, pe);
pe               1606 arch/powerpc/platforms/powernv/pci-ioda.c 		iommu_register_group(&pe->table_group,
pe               1607 arch/powerpc/platforms/powernv/pci-ioda.c 				pe->phb->hose->global_number, pe->pe_number);
pe               1608 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
pe               1618 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe    *pe;
pe               1662 arch/powerpc/platforms/powernv/pci-ioda.c 				pe = pnv_ioda_alloc_pe(phb);
pe               1663 arch/powerpc/platforms/powernv/pci-ioda.c 				if (!pe) {
pe               1668 arch/powerpc/platforms/powernv/pci-ioda.c 				pdn->pe_num_map[i] = pe->pe_number;
pe               1716 arch/powerpc/platforms/powernv/pci-ioda.c 			pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
pe               1717 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_free_pe(pe);
pe               1749 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               1759 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = &phb->ioda.pe_array[pdn->pe_number];
pe               1761 arch/powerpc/platforms/powernv/pci-ioda.c 	pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
pe               1762 arch/powerpc/platforms/powernv/pci-ioda.c 	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
pe               1788 arch/powerpc/platforms/powernv/pci-ioda.c static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
pe               1807 arch/powerpc/platforms/powernv/pci-ioda.c 	table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
pe               1823 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
pe               1824 arch/powerpc/platforms/powernv/pci-ioda.c 					pe->pe_number,
pe               1826 arch/powerpc/platforms/powernv/pci-ioda.c 					(pe->pe_number << 1) + 0,
pe               1832 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
pe               1836 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_err(pe, "Error configuring 64-bit DMA bypass\n");
pe               1846 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               1851 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = &phb->ioda.pe_array[pdn->pe_number];
pe               1852 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->tce_bypass_enabled) {
pe               1853 arch/powerpc/platforms/powernv/pci-ioda.c 		u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
pe               1867 arch/powerpc/platforms/powernv/pci-ioda.c 	    (pe->device_count == 1 || !pe->pbus) &&
pe               1870 arch/powerpc/platforms/powernv/pci-ioda.c 		s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
pe               1881 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
pe               1886 arch/powerpc/platforms/powernv/pci-ioda.c 		set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
pe               1887 arch/powerpc/platforms/powernv/pci-ioda.c 		dev->dev.archdata.dma_offset = pe->tce_bypass_base;
pe               1889 arch/powerpc/platforms/powernv/pci-ioda.c 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
pe               1890 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_setup_bus_dma(pe, dev->subordinate);
pe               1907 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(tgl->table_group,
pe               1909 arch/powerpc/platforms/powernv/pci-ioda.c 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
pe               1997 arch/powerpc/platforms/powernv/pci-ioda.c static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
pe               2000 arch/powerpc/platforms/powernv/pci-ioda.c 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
pe               2001 arch/powerpc/platforms/powernv/pci-ioda.c 	unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
pe               2007 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
pe               2011 arch/powerpc/platforms/powernv/pci-ioda.c 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
pe               2016 arch/powerpc/platforms/powernv/pci-ioda.c 	start |= (pe->pe_number & 0xFF);
pe               2034 arch/powerpc/platforms/powernv/pci-ioda.c static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
pe               2036 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               2039 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_phb3_tce_invalidate_pe(pe);
pe               2042 arch/powerpc/platforms/powernv/pci-ioda.c 				  pe->pe_number, 0, 0, 0);
pe               2051 arch/powerpc/platforms/powernv/pci-ioda.c 		struct pnv_ioda_pe *pe = container_of(tgl->table_group,
pe               2053 arch/powerpc/platforms/powernv/pci-ioda.c 		struct pnv_phb *phb = pe->phb;
pe               2071 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_pci_phb3_tce_invalidate(pe, rm, shift,
pe               2076 arch/powerpc/platforms/powernv/pci-ioda.c 					  pe->pe_number, 1u << shift,
pe               2145 arch/powerpc/platforms/powernv/pci-ioda.c static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
pe               2151 arch/powerpc/platforms/powernv/pci-ioda.c 	if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
pe               2152 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
pe               2157 arch/powerpc/platforms/powernv/pci-ioda.c 	if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
pe               2158 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
pe               2159 arch/powerpc/platforms/powernv/pci-ioda.c 	} else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
pe               2162 arch/powerpc/platforms/powernv/pci-ioda.c 		list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
pe               2164 arch/powerpc/platforms/powernv/pci-ioda.c 	} else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
pe               2165 arch/powerpc/platforms/powernv/pci-ioda.c 		pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
pe               2172 arch/powerpc/platforms/powernv/pci-ioda.c 				       struct pnv_ioda_pe *pe)
pe               2185 arch/powerpc/platforms/powernv/pci-ioda.c 	weight = pnv_pci_ioda_pe_dma_weight(pe);
pe               2215 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_warn(pe, "No available DMA32 segments\n");
pe               2224 arch/powerpc/platforms/powernv/pci-ioda.c 	iommu_register_group(&pe->table_group, phb->hose->global_number,
pe               2225 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->pe_number);
pe               2226 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
pe               2229 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
pe               2231 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
pe               2247 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
pe               2256 arch/powerpc/platforms/powernv/pci-ioda.c 					      pe->pe_number,
pe               2261 arch/powerpc/platforms/powernv/pci-ioda.c 			pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
pe               2269 arch/powerpc/platforms/powernv/pci-ioda.c 		phb->ioda.dma32_segmap[i] = pe->pe_number;
pe               2277 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
pe               2278 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
pe               2281 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
pe               2282 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
pe               2290 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
pe               2298 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
pe               2300 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               2307 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
pe               2316 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->pe_number,
pe               2317 arch/powerpc/platforms/powernv/pci-ioda.c 			(pe->pe_number << 1) + num,
pe               2323 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
pe               2328 arch/powerpc/platforms/powernv/pci-ioda.c 			tbl, &pe->table_group);
pe               2329 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_ioda2_tce_invalidate_pe(pe);
pe               2334 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
pe               2336 arch/powerpc/platforms/powernv/pci-ioda.c 	uint16_t window_id = (pe->pe_number << 1 ) + 1;
pe               2339 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
pe               2344 arch/powerpc/platforms/powernv/pci-ioda.c 		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
pe               2345 arch/powerpc/platforms/powernv/pci-ioda.c 						     pe->pe_number,
pe               2347 arch/powerpc/platforms/powernv/pci-ioda.c 						     pe->tce_bypass_base,
pe               2350 arch/powerpc/platforms/powernv/pci-ioda.c 		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
pe               2351 arch/powerpc/platforms/powernv/pci-ioda.c 						     pe->pe_number,
pe               2353 arch/powerpc/platforms/powernv/pci-ioda.c 						     pe->tce_bypass_base,
pe               2357 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
pe               2359 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->tce_bypass_enabled = enable;
pe               2366 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
pe               2368 arch/powerpc/platforms/powernv/pci-ioda.c 	int nid = pe->phb->hose->node;
pe               2369 arch/powerpc/platforms/powernv/pci-ioda.c 	__u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
pe               2392 arch/powerpc/platforms/powernv/pci-ioda.c static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
pe               2434 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
pe               2437 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
pe               2445 arch/powerpc/platforms/powernv/pci-ioda.c 	if (window_size > pe->phb->ioda.m32_pci_base) {
pe               2446 arch/powerpc/platforms/powernv/pci-ioda.c 		res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
pe               2449 arch/powerpc/platforms/powernv/pci-ioda.c 	iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end);
pe               2451 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
pe               2453 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
pe               2460 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda2_set_bypass(pe, true);
pe               2467 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->pdev)
pe               2468 arch/powerpc/platforms/powernv/pci-ioda.c 		set_iommu_table_base(&pe->pdev->dev, tbl);
pe               2477 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
pe               2479 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               2482 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "Removing DMA window #%d\n", num);
pe               2484 arch/powerpc/platforms/powernv/pci-ioda.c 	ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
pe               2485 arch/powerpc/platforms/powernv/pci-ioda.c 			(pe->pe_number << 1) + num,
pe               2489 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
pe               2491 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda2_tce_invalidate_pe(pe);
pe               2548 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
pe               2551 arch/powerpc/platforms/powernv/pci-ioda.c 	struct iommu_table *tbl = pe->table_group.tables[0];
pe               2553 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_ioda2_set_bypass(pe, false);
pe               2554 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_ioda2_unset_window(&pe->table_group, 0);
pe               2555 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->pbus)
pe               2556 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
pe               2557 arch/powerpc/platforms/powernv/pci-ioda.c 	else if (pe->pdev)
pe               2558 arch/powerpc/platforms/powernv/pci-ioda.c 		set_iommu_table_base(&pe->pdev->dev, NULL);
pe               2564 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
pe               2567 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_ioda2_setup_default_config(pe);
pe               2568 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->pbus)
pe               2569 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
pe               2581 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
pe               2590 arch/powerpc/platforms/powernv/pci-ioda.c 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
pe               2591 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_setup_bus_iommu_group_add_devices(pe,
pe               2596 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
pe               2600 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_DEV)
pe               2601 arch/powerpc/platforms/powernv/pci-ioda.c 		iommu_add_device(table_group, &pe->pdev->dev);
pe               2603 arch/powerpc/platforms/powernv/pci-ioda.c 	if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
pe               2604 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
pe               2614 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               2637 arch/powerpc/platforms/powernv/pci-ioda.c 		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
pe               2640 arch/powerpc/platforms/powernv/pci-ioda.c 			table_group = pnv_try_setup_npu_table_group(pe);
pe               2642 arch/powerpc/platforms/powernv/pci-ioda.c 				if (!pnv_pci_ioda_pe_dma_weight(pe))
pe               2645 arch/powerpc/platforms/powernv/pci-ioda.c 				table_group = &pe->table_group;
pe               2646 arch/powerpc/platforms/powernv/pci-ioda.c 				iommu_register_group(&pe->table_group,
pe               2647 arch/powerpc/platforms/powernv/pci-ioda.c 						pe->phb->hose->global_number,
pe               2648 arch/powerpc/platforms/powernv/pci-ioda.c 						pe->pe_number);
pe               2650 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_setup_bus_iommu_group(pe, table_group,
pe               2651 arch/powerpc/platforms/powernv/pci-ioda.c 					pe->pbus);
pe               2668 arch/powerpc/platforms/powernv/pci-ioda.c 		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
pe               2674 arch/powerpc/platforms/powernv/pci-ioda.c 			pe->table_group.pgsizes = pgsizes;
pe               2675 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_npu_compound_attach(pe);
pe               2712 arch/powerpc/platforms/powernv/pci-ioda.c 				       struct pnv_ioda_pe *pe)
pe               2716 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!pnv_pci_ioda_pe_dma_weight(pe))
pe               2720 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->tce_bypass_base = 1ull << 59;
pe               2723 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
pe               2727 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.tce32_start = 0;
pe               2728 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.tce32_size = phb->ioda.m32_pci_base;
pe               2729 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.max_dynamic_windows_supported =
pe               2731 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
pe               2732 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
pe               2734 arch/powerpc/platforms/powernv/pci-ioda.c 	pe->table_group.ops = &pnv_pci_ioda2_ops;
pe               2737 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = pnv_pci_ioda2_setup_default_config(pe);
pe               2741 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
pe               2742 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
pe               2803 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
pe               2809 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe == NULL)
pe               2813 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->mve_number < 0)
pe               2821 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
pe               2831 arch/powerpc/platforms/powernv/pci-ioda.c 		rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
pe               2843 arch/powerpc/platforms/powernv/pci-ioda.c 		rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
pe               2860 arch/powerpc/platforms/powernv/pci-ioda.c 		 msg->address_hi, msg->address_lo, data, pe->pe_number);
pe               2984 arch/powerpc/platforms/powernv/pci-ioda.c 		struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
pe               2991 arch/powerpc/platforms/powernv/pci-ioda.c 		pe->pdev = pdev;
pe               2992 arch/powerpc/platforms/powernv/pci-ioda.c 		WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
pe               3003 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
pe               3006 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               3021 arch/powerpc/platforms/powernv/pci-ioda.c 			phb->ioda.io_segmap[index] = pe->pe_number;
pe               3023 arch/powerpc/platforms/powernv/pci-ioda.c 				pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
pe               3026 arch/powerpc/platforms/powernv/pci-ioda.c 				       __func__, rc, index, pe->pe_number);
pe               3045 arch/powerpc/platforms/powernv/pci-ioda.c 			phb->ioda.m32_segmap[index] = pe->pe_number;
pe               3047 arch/powerpc/platforms/powernv/pci-ioda.c 				pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
pe               3050 arch/powerpc/platforms/powernv/pci-ioda.c 				       __func__, rc, index, pe->pe_number);
pe               3065 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
pe               3075 arch/powerpc/platforms/powernv/pci-ioda.c 	BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
pe               3077 arch/powerpc/platforms/powernv/pci-ioda.c 	list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
pe               3079 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
pe               3086 arch/powerpc/platforms/powernv/pci-ioda.c 		if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
pe               3089 arch/powerpc/platforms/powernv/pci-ioda.c 			pnv_ioda_setup_pe_res(pe,
pe               3308 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               3316 arch/powerpc/platforms/powernv/pci-ioda.c 		pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
pe               3317 arch/powerpc/platforms/powernv/pci-ioda.c 		if (pe) {
pe               3318 arch/powerpc/platforms/powernv/pci-ioda.c 			phb->ioda.root_pe_idx = pe->pe_number;
pe               3335 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = pnv_ioda_setup_bus_PE(bus, all);
pe               3336 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!pe)
pe               3339 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_ioda_setup_pe_seg(pe);
pe               3342 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda1_setup_dma_pe(phb, pe);
pe               3345 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda2_setup_dma_pe(phb, pe);
pe               3421 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe = container_of(table_group,
pe               3423 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               3427 arch/powerpc/platforms/powernv/pci-ioda.c 	pe_info(pe, "Removing DMA window #%d\n", num);
pe               3429 arch/powerpc/platforms/powernv/pci-ioda.c 		if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
pe               3432 arch/powerpc/platforms/powernv/pci-ioda.c 		rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
pe               3435 arch/powerpc/platforms/powernv/pci-ioda.c 			pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
pe               3447 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
pe               3449 arch/powerpc/platforms/powernv/pci-ioda.c 	unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
pe               3450 arch/powerpc/platforms/powernv/pci-ioda.c 	struct iommu_table *tbl = pe->table_group.tables[0];
pe               3456 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
pe               3461 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->table_group.group) {
pe               3462 arch/powerpc/platforms/powernv/pci-ioda.c 		iommu_group_put(pe->table_group.group);
pe               3463 arch/powerpc/platforms/powernv/pci-ioda.c 		WARN_ON(pe->table_group.group);
pe               3470 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
pe               3472 arch/powerpc/platforms/powernv/pci-ioda.c 	struct iommu_table *tbl = pe->table_group.tables[0];
pe               3473 arch/powerpc/platforms/powernv/pci-ioda.c 	unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
pe               3482 arch/powerpc/platforms/powernv/pci-ioda.c 	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
pe               3484 arch/powerpc/platforms/powernv/pci-ioda.c 		pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
pe               3487 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_pci_ioda2_set_bypass(pe, false);
pe               3488 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->table_group.group) {
pe               3489 arch/powerpc/platforms/powernv/pci-ioda.c 		iommu_group_put(pe->table_group.group);
pe               3490 arch/powerpc/platforms/powernv/pci-ioda.c 		WARN_ON(pe->table_group.group);
pe               3496 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
pe               3500 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               3505 arch/powerpc/platforms/powernv/pci-ioda.c 		if (map[idx] != pe->pe_number)
pe               3518 arch/powerpc/platforms/powernv/pci-ioda.c 			pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
pe               3525 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
pe               3527 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               3530 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
pe               3532 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
pe               3534 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
pe               3537 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
pe               3542 arch/powerpc/platforms/powernv/pci-ioda.c static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
pe               3544 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_phb *phb = pe->phb;
pe               3547 arch/powerpc/platforms/powernv/pci-ioda.c 	list_del(&pe->list);
pe               3550 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda1_release_pe_dma(pe);
pe               3553 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_pci_ioda2_release_pe_dma(pe);
pe               3559 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_ioda_release_pe_seg(pe);
pe               3560 arch/powerpc/platforms/powernv/pci-ioda.c 	pnv_ioda_deconfigure_pe(pe->phb, pe);
pe               3563 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->flags & PNV_IODA_PE_MASTER) {
pe               3564 arch/powerpc/platforms/powernv/pci-ioda.c 		list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
pe               3577 arch/powerpc/platforms/powernv/pci-ioda.c 	    phb->ioda.root_pe_idx == pe->pe_number)
pe               3580 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_free_pe(pe);
pe               3588 arch/powerpc/platforms/powernv/pci-ioda.c 	struct pnv_ioda_pe *pe;
pe               3604 arch/powerpc/platforms/powernv/pci-ioda.c 	pe = &phb->ioda.pe_array[pdn->pe_number];
pe               3607 arch/powerpc/platforms/powernv/pci-ioda.c 	WARN_ON(--pe->device_count < 0);
pe               3608 arch/powerpc/platforms/powernv/pci-ioda.c 	if (pe->device_count == 0)
pe               3609 arch/powerpc/platforms/powernv/pci-ioda.c 		pnv_ioda_release_pe(pe);
pe               3615 arch/powerpc/platforms/powernv/pci-ioda.c 	struct eeh_pe *eehpe = edev ? edev->pe : NULL;
pe                725 arch/powerpc/platforms/powernv/pci.c 		if (edev->pe &&
pe                726 arch/powerpc/platforms/powernv/pci.c 		    (edev->pe->state & EEH_PE_CFG_BLOCKED))
pe                826 arch/powerpc/platforms/powernv/pci.c 	struct pnv_ioda_pe *pe;
pe                828 arch/powerpc/platforms/powernv/pci.c 	list_for_each_entry(pe, &phb->ioda.pe_list, list) {
pe                829 arch/powerpc/platforms/powernv/pci.c 		if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
pe                832 arch/powerpc/platforms/powernv/pci.c 		if (!pe->pbus)
pe                835 arch/powerpc/platforms/powernv/pci.c 		if (bus->number == ((pe->rid >> 8) & 0xFF)) {
pe                836 arch/powerpc/platforms/powernv/pci.c 			pe->pbus = bus;
pe                985 arch/powerpc/platforms/powernv/pci.c 	struct pnv_ioda_pe *pe;
pe               1000 arch/powerpc/platforms/powernv/pci.c 		pe = &phb->ioda.pe_array[pdn->pe_number];
pe               1001 arch/powerpc/platforms/powernv/pci.c 		if (!pe->table_group.group)
pe               1003 arch/powerpc/platforms/powernv/pci.c 		iommu_add_device(&pe->table_group, dev);
pe                203 arch/powerpc/platforms/powernv/pci.h extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
pe                205 arch/powerpc/platforms/powernv/pci.h #define pe_err(pe, fmt, ...)					\
pe                206 arch/powerpc/platforms/powernv/pci.h 	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
pe                207 arch/powerpc/platforms/powernv/pci.h #define pe_warn(pe, fmt, ...)					\
pe                208 arch/powerpc/platforms/powernv/pci.h 	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
pe                209 arch/powerpc/platforms/powernv/pci.h #define pe_info(pe, fmt, ...)					\
pe                210 arch/powerpc/platforms/powernv/pci.h 	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
pe                217 arch/powerpc/platforms/powernv/pci.h 		struct pnv_ioda_pe *pe);
pe                219 arch/powerpc/platforms/powernv/pci.h 		struct pnv_ioda_pe *pe);
pe                236 arch/powerpc/platforms/pseries/eeh_pseries.c 	struct eeh_pe pe;
pe                243 arch/powerpc/platforms/pseries/eeh_pseries.c 	if (!edev || edev->pe)
pe                280 arch/powerpc/platforms/pseries/eeh_pseries.c 	memset(&pe, 0, sizeof(struct eeh_pe));
pe                281 arch/powerpc/platforms/pseries/eeh_pseries.c 	pe.phb = pdn->phb;
pe                282 arch/powerpc/platforms/pseries/eeh_pseries.c 	pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
pe                286 arch/powerpc/platforms/pseries/eeh_pseries.c 	ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
pe                291 arch/powerpc/platforms/pseries/eeh_pseries.c 		edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
pe                292 arch/powerpc/platforms/pseries/eeh_pseries.c 		pe.addr = edev->pe_config_addr;
pe                298 arch/powerpc/platforms/pseries/eeh_pseries.c 		ret = eeh_ops->get_state(&pe, NULL);
pe                306 arch/powerpc/platforms/pseries/eeh_pseries.c 			   (pdn_to_eeh_dev(pdn->parent))->pe) {
pe                332 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
pe                348 arch/powerpc/platforms/pseries/eeh_pseries.c 		config_addr = pe->config_addr;
pe                349 arch/powerpc/platforms/pseries/eeh_pseries.c 		if (pe->addr)
pe                350 arch/powerpc/platforms/pseries/eeh_pseries.c 			config_addr = pe->addr;
pe                362 arch/powerpc/platforms/pseries/eeh_pseries.c 			config_addr, BUID_HI(pe->phb->buid),
pe                363 arch/powerpc/platforms/pseries/eeh_pseries.c 			BUID_LO(pe->phb->buid), option);
pe                381 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_get_pe_addr(struct eeh_pe *pe)
pe                393 arch/powerpc/platforms/pseries/eeh_pseries.c 				pe->config_addr, BUID_HI(pe->phb->buid),
pe                394 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid), 1);
pe                400 arch/powerpc/platforms/pseries/eeh_pseries.c 				pe->config_addr, BUID_HI(pe->phb->buid),
pe                401 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid), 0);
pe                404 arch/powerpc/platforms/pseries/eeh_pseries.c 				__func__, pe->phb->global_number, pe->config_addr);
pe                413 arch/powerpc/platforms/pseries/eeh_pseries.c 				pe->config_addr, BUID_HI(pe->phb->buid),
pe                414 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid), 0);
pe                417 arch/powerpc/platforms/pseries/eeh_pseries.c 				__func__, pe->phb->global_number, pe->config_addr);
pe                440 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)
pe                448 arch/powerpc/platforms/pseries/eeh_pseries.c 	config_addr = pe->config_addr;
pe                449 arch/powerpc/platforms/pseries/eeh_pseries.c 	if (pe->addr)
pe                450 arch/powerpc/platforms/pseries/eeh_pseries.c 		config_addr = pe->addr;
pe                454 arch/powerpc/platforms/pseries/eeh_pseries.c 				config_addr, BUID_HI(pe->phb->buid),
pe                455 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid));
pe                460 arch/powerpc/platforms/pseries/eeh_pseries.c 				config_addr, BUID_HI(pe->phb->buid),
pe                461 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid));
pe                512 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_reset(struct eeh_pe *pe, int option)
pe                518 arch/powerpc/platforms/pseries/eeh_pseries.c 	config_addr = pe->config_addr;
pe                519 arch/powerpc/platforms/pseries/eeh_pseries.c 	if (pe->addr)
pe                520 arch/powerpc/platforms/pseries/eeh_pseries.c 		config_addr = pe->addr;
pe                524 arch/powerpc/platforms/pseries/eeh_pseries.c 			config_addr, BUID_HI(pe->phb->buid),
pe                525 arch/powerpc/platforms/pseries/eeh_pseries.c 			BUID_LO(pe->phb->buid), option);
pe                532 arch/powerpc/platforms/pseries/eeh_pseries.c 				config_addr, BUID_HI(pe->phb->buid),
pe                533 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid), option);
pe                557 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
pe                567 arch/powerpc/platforms/pseries/eeh_pseries.c 	config_addr = pe->config_addr;
pe                568 arch/powerpc/platforms/pseries/eeh_pseries.c 	if (pe->addr)
pe                569 arch/powerpc/platforms/pseries/eeh_pseries.c 		config_addr = pe->addr;
pe                572 arch/powerpc/platforms/pseries/eeh_pseries.c 			BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
pe                591 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
pe                599 arch/powerpc/platforms/pseries/eeh_pseries.c 	config_addr = pe->config_addr;
pe                600 arch/powerpc/platforms/pseries/eeh_pseries.c 	if (pe->addr)
pe                601 arch/powerpc/platforms/pseries/eeh_pseries.c 		config_addr = pe->addr;
pe                605 arch/powerpc/platforms/pseries/eeh_pseries.c 				config_addr, BUID_HI(pe->phb->buid),
pe                606 arch/powerpc/platforms/pseries/eeh_pseries.c 				BUID_LO(pe->phb->buid));
pe                629 arch/powerpc/platforms/pseries/eeh_pseries.c 		__func__, pe->phb->global_number, pe->addr, ret);
pe                200 arch/powerpc/platforms/pseries/msi.c 	if (edev->pe)
pe                201 arch/powerpc/platforms/pseries/msi.c 		edev = list_first_entry(&edev->pe->edevs, struct eeh_dev,
pe               2703 arch/x86/kvm/lapic.c 	unsigned long pe;
pe               2723 arch/x86/kvm/lapic.c 	pe = xchg(&apic->pending_events, 0);
pe               2724 arch/x86/kvm/lapic.c 	if (test_bit(KVM_APIC_INIT, &pe)) {
pe               2731 arch/x86/kvm/lapic.c 	if (test_bit(KVM_APIC_SIPI, &pe) &&
pe                 26 crypto/asymmetric_keys/verify_pefile.c 	const struct pe_hdr *pe;
pe                 47 crypto/asymmetric_keys/verify_pefile.c 	chkaddr(cursor, mz->peaddr, sizeof(*pe));
pe                 48 crypto/asymmetric_keys/verify_pefile.c 	pe = pebuf + mz->peaddr;
pe                 49 crypto/asymmetric_keys/verify_pefile.c 	if (pe->magic != PE_MAGIC)
pe                 51 crypto/asymmetric_keys/verify_pefile.c 	cursor = mz->peaddr + sizeof(*pe);
pe                110 crypto/asymmetric_keys/verify_pefile.c 	ctx->n_sections = pe->sections;
pe                136 drivers/ata/sata_dwc_460ex.c 	struct ata_probe_ent	*pe;		/* ptr to probe-ent */
pe                766 drivers/atm/firestream.c 	struct FS_BPENTRY *pe;    
pe                782 drivers/atm/firestream.c 		pe = bus_to_virt (qe->p0);
pe                784 drivers/atm/firestream.c 			    pe->flags, pe->next, pe->bsa, pe->aal_bufsize, 
pe                785 drivers/atm/firestream.c 			    pe->skb, pe->fp);
pe                800 drivers/atm/firestream.c 				skb = pe->skb;
pe                801 drivers/atm/firestream.c 				pe->fp->n--;
pe                804 drivers/atm/firestream.c 				if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
pe                812 drivers/atm/firestream.c 				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
pe                813 drivers/atm/firestream.c 				kfree (pe);
pe                821 drivers/atm/firestream.c 				pe = bus_to_virt (qe->p0);
pe                822 drivers/atm/firestream.c 				pe->fp->n--;
pe                823 drivers/atm/firestream.c 				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
pe                824 drivers/atm/firestream.c 				dev_kfree_skb_any (pe->skb);
pe                825 drivers/atm/firestream.c 				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
pe                826 drivers/atm/firestream.c 				kfree (pe);
pe                 36 drivers/clk/st/clkgen-fsyn.c 	unsigned long pe;
pe                 59 drivers/clk/st/clkgen-fsyn.c 	struct clkgen_field pe[QUADFS_MAX_CHAN];
pe                101 drivers/clk/st/clkgen-fsyn.c 	.pe	= { CLKGEN_FIELD(0x304, 0x7fff, 0),
pe                125 drivers/clk/st/clkgen-fsyn.c 	.pe	= { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
pe                463 drivers/clk/st/clkgen-fsyn.c 	u32 pe;
pe                493 drivers/clk/st/clkgen-fsyn.c 	CLKGEN_WRITE(fs, pe[fs->chan], fs->pe);
pe                577 drivers/clk/st/clkgen-fsyn.c 	res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns;
pe                602 drivers/clk/st/clkgen-fsyn.c 	fs_tmp.pe = (unsigned long)*p;
pe                612 drivers/clk/st/clkgen-fsyn.c 		fs->pe = (unsigned long)*p;
pe                661 drivers/clk/st/clkgen-fsyn.c 		if (fs->pe > 2)
pe                662 drivers/clk/st/clkgen-fsyn.c 			p2 = fs->pe - 2;
pe                666 drivers/clk/st/clkgen-fsyn.c 		for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) {
pe                667 drivers/clk/st/clkgen-fsyn.c 			fs_tmp.pe = (unsigned long)p2;
pe                675 drivers/clk/st/clkgen-fsyn.c 				fs->pe = (unsigned long)p2;
pe                691 drivers/clk/st/clkgen-fsyn.c 	params->pe	= CLKGEN_READ(fs, pe[fs->chan]);
pe                702 drivers/clk/st/clkgen-fsyn.c 	if (!params->mdiv && !params->pe && !params->sdiv)
pe                706 drivers/clk/st/clkgen-fsyn.c 	fs->pe = params->pe;
pe                765 drivers/clk/st/clkgen-fsyn.c 			 (unsigned int)params.pe, (unsigned int)params.nsdiv);
pe                775 drivers/clk/st/clkgen-fsyn.c 	fs->pe = params->pe;
pe                258 drivers/crypto/inside-secure/safexcel.c 	int pe, i;
pe                261 drivers/crypto/inside-secure/safexcel.c 	for (pe = 0; pe < priv->config.pes; pe++) {
pe                263 drivers/crypto/inside-secure/safexcel.c 		writel(3, EIP197_PE(priv) + EIP197_PE_ICE_PUTF_CTRL(pe));
pe                264 drivers/crypto/inside-secure/safexcel.c 		writel(0, EIP197_PE(priv) + EIP197_PE_ICE_PPTF_CTRL(pe));
pe                267 drivers/crypto/inside-secure/safexcel.c 		val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
pe                272 drivers/crypto/inside-secure/safexcel.c 		writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
pe                277 drivers/crypto/inside-secure/safexcel.c 				  EIP197_PE_ICE_SCRATCH_RAM(pe) + (i << 2));
pe                283 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));
pe                289 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));
pe                293 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
pe                319 drivers/crypto/inside-secure/safexcel.c 	int pe, pollcnt;
pe                327 drivers/crypto/inside-secure/safexcel.c 	for (pe = 0; pe < priv->config.pes; pe++) {
pe                328 drivers/crypto/inside-secure/safexcel.c 		base = EIP197_PE_ICE_SCRATCH_RAM(pe);
pe                337 drivers/crypto/inside-secure/safexcel.c 				fpp, pe);
pe                347 drivers/crypto/inside-secure/safexcel.c 	int pe;
pe                350 drivers/crypto/inside-secure/safexcel.c 	for (pe = 0; pe < priv->config.pes; pe++) {
pe                352 drivers/crypto/inside-secure/safexcel.c 		writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
pe                361 drivers/crypto/inside-secure/safexcel.c 		writel(val, EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));
pe                370 drivers/crypto/inside-secure/safexcel.c 		writel(val, EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));
pe                391 drivers/crypto/inside-secure/safexcel.c 	int i, j, ret = 0, pe;
pe                425 drivers/crypto/inside-secure/safexcel.c 	for (pe = 0; pe < priv->config.pes; pe++)
pe                427 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
pe                562 drivers/crypto/inside-secure/safexcel.c 	int i, ret, pe;
pe                591 drivers/crypto/inside-secure/safexcel.c 	for (pe = 0; pe < priv->config.pes; pe++) {
pe                596 drivers/crypto/inside-secure/safexcel.c 		       EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
pe                601 drivers/crypto/inside-secure/safexcel.c 			       EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));
pe                611 drivers/crypto/inside-secure/safexcel.c 		writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG(pe));
pe                614 drivers/crypto/inside-secure/safexcel.c 		writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
pe                619 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_IN_DBUF_THRES(pe));
pe                622 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_IN_TBUF_THRES(pe));
pe                628 drivers/crypto/inside-secure/safexcel.c 			       EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));
pe                634 drivers/crypto/inside-secure/safexcel.c 		       EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
pe                637 drivers/crypto/inside-secure/safexcel.c 		while ((readl(EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_STAT(pe)) &
pe                652 drivers/crypto/inside-secure/safexcel.c 		writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG(pe));
pe                655 drivers/crypto/inside-secure/safexcel.c 		writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
pe                660 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_OUT_DBUF_THRES(pe));
pe                668 drivers/crypto/inside-secure/safexcel.c 		writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL(pe));
pe                672 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_EIP96_FUNCTION_EN(pe));
pe                674 drivers/crypto/inside-secure/safexcel.c 		       EIP197_PE(priv) + EIP197_PE_EIP96_FUNCTION2_EN(pe));
pe                726 drivers/crypto/inside-secure/safexcel.c 	for (pe = 0; pe < priv->config.pes; pe++) {
pe                729 drivers/crypto/inside-secure/safexcel.c 		       EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
pe                733 drivers/crypto/inside-secure/safexcel.c 		       EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
pe               1283 drivers/crypto/inside-secure/safexcel.c 		offsets->pe		= EIP197_PE_BASE;
pe               1295 drivers/crypto/inside-secure/safexcel.c 		offsets->pe		= EIP97_PE_BASE;
pe                 81 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE(priv)			((priv)->base + (priv)->offsets.pe)
pe                693 drivers/crypto/inside-secure/safexcel.h 	u32 pe;
pe                 64 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
pe                 74 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	switch (pe->pmu_perf_type) {
pe                 77 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 			pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
pe                 79 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 		pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
pe                 93 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
pe                102 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 		switch (pe->pmu_perf_type) {
pe                104 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 			pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf,
pe                120 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
pe                127 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	switch (pe->pmu_perf_type) {
pe                129 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 		pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
pe                151 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
pe                157 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	switch (pe->pmu_perf_type) {
pe                159 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 		retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
pe                179 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
pe                185 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	switch (pe->pmu_perf_type) {
pe                187 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 		pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
pe                271 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	struct amdgpu_pmu_entry *pe, *temp;
pe                273 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 	list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {
pe                274 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 		if (pe->adev == adev) {
pe                275 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 			list_del(&pe->entry);
pe                276 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 			perf_pmu_unregister(&pe->pmu);
pe                277 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 			kfree(pe);
pe                325 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 	    TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
pe                327 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 	    TP_ARGS(pe, addr, count, incr, flags),
pe                329 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 			     __field(u64, pe)
pe                337 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 			   __entry->pe = pe;
pe                344 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 		      __entry->pe, __entry->addr, __entry->incr,
pe                349 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 	    TP_PROTO(uint64_t pe, uint64_t src, unsigned count),
pe                350 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 	    TP_ARGS(pe, src, count),
pe                352 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 			     __field(u64, pe)
pe                358 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 			   __entry->pe = pe;
pe                363 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 		      __entry->pe, __entry->src, __entry->count)
pe               1284 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 				   uint64_t pe, uint64_t addr,
pe               1301 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 	params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
pe                161 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 			 uint64_t pe, uint64_t src,
pe                165 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
pe                170 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 			    uint64_t pe,
pe                224 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 		      struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
pe                336 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
pe                337 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
pe                338 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
pe                 83 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c 				struct amdgpu_bo *bo, uint64_t pe,
pe                 90 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c 	pe += (unsigned long)amdgpu_bo_kptr(bo);
pe                 92 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c 	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
pe                 98 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c 		amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
pe                135 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 				     struct amdgpu_bo *bo, uint64_t pe,
pe                143 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 	pe += amdgpu_bo_gpu_offset(bo);
pe                144 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 	trace_amdgpu_vm_copy_ptes(pe, src, count);
pe                146 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 	amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
pe                164 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 				    struct amdgpu_bo *bo, uint64_t pe,
pe                170 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 	pe += amdgpu_bo_gpu_offset(bo);
pe                171 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
pe                173 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 		amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
pe                176 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 		amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr,
pe                196 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 				 struct amdgpu_bo *bo, uint64_t pe,
pe                230 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 				amdgpu_vm_sdma_set_ptes(p, bo->shadow, pe, addr,
pe                232 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 			amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
pe                255 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 			amdgpu_vm_sdma_copy_ptes(p, bo->shadow, pe, nptes);
pe                256 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 		amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
pe                258 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 		pe += nptes * 8;
pe                729 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 				 uint64_t pe, uint64_t src,
pe                740 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                741 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                755 drivers/gpu/drm/amd/amdgpu/cik_sdma.c static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
pe                763 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                764 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                785 drivers/gpu/drm/amd/amdgpu/cik_sdma.c static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
pe                791 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
pe                792 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                668 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 				  uint64_t pe, uint64_t src,
pe                679 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                680 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                694 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
pe                702 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	ib->ptr[ib->length_dw++] = pe;
pe                703 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                724 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
pe                730 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
pe                731 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                939 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 				  uint64_t pe, uint64_t src,
pe                950 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                951 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                965 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
pe                973 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                974 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                995 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
pe               1001 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
pe               1002 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe               1494 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 				  uint64_t pe, uint64_t src,
pe               1505 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe               1506 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe               1522 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
pe               1530 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe               1531 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe               1553 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 				     uint64_t pe,
pe               1559 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
pe               1560 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe               1031 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 				  uint64_t pe, uint64_t src,
pe               1042 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe               1043 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe               1059 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
pe               1067 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe               1068 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe               1090 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 				     uint64_t pe,
pe               1096 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
pe               1097 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                315 drivers/gpu/drm/amd/amdgpu/si_dma.c 			       uint64_t pe, uint64_t src,
pe                322 drivers/gpu/drm/amd/amdgpu/si_dma.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                324 drivers/gpu/drm/amd/amdgpu/si_dma.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                339 drivers/gpu/drm/amd/amdgpu/si_dma.c static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
pe                346 drivers/gpu/drm/amd/amdgpu/si_dma.c 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                347 drivers/gpu/drm/amd/amdgpu/si_dma.c 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                368 drivers/gpu/drm/amd/amdgpu/si_dma.c 				     uint64_t pe,
pe                387 drivers/gpu/drm/amd/amdgpu/si_dma.c 		ib->ptr[ib->length_dw++] = pe; /* dst addr */
pe                388 drivers/gpu/drm/amd/amdgpu/si_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                395 drivers/gpu/drm/amd/amdgpu/si_dma.c 		pe += ndw * 4;
pe                399 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 		struct dpu_hw_pixel_ext *pe,
pe                405 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	(void)pe;
pe                253 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 	struct dpu_drm_pix_ext_v1 pe;
pe                820 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 				 struct pixel_ext *pe,
pe                883 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 				src_w, pe->left, pe->right,
pe                884 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 				src_h, pe->top, pe->bottom);
pe                925 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct pixel_ext pe = { { 0 } };
pe                991 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			       pe.left, pe.right, true);
pe                993 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			       pe.top, pe.bottom, false);
pe               1010 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
pe               1016 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 		mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
pe                 26 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h 	u8 pe;
pe                 34 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h nvbios_dpcfg_match(struct nvkm_bios *, u16 outp, u8 pc, u8 vs, u8 pe,
pe                123 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 					    ocfg.pe, ocfg.tx_pu);
pe                 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h 			      int dc, int pe, int tx_pu);
pe                 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
pe                 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
pe                 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
pe                 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
pe                 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
pe                 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c 	nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
pe                182 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			info->pe    = nvbios_rd08(bios, data + 0x03);
pe                190 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			info->pe    = nvbios_rd08(bios, data + 0x02);
pe                195 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			info->pe    = nvbios_rd08(bios, data + 0x01);
pe                207 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
pe                216 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 		idx = (pc * 10) + vsoff[vs] + pe;
pe                226 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			    nvbios_rd08(bios, data + 0x01) == pe)
pe                805 drivers/gpu/drm/radeon/cik_sdma.c 			    uint64_t pe, uint64_t src,
pe                819 drivers/gpu/drm/radeon/cik_sdma.c 		ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                820 drivers/gpu/drm/radeon/cik_sdma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                822 drivers/gpu/drm/radeon/cik_sdma.c 		pe += bytes;
pe                843 drivers/gpu/drm/radeon/cik_sdma.c 			     uint64_t pe,
pe                858 drivers/gpu/drm/radeon/cik_sdma.c 		ib->ptr[ib->length_dw++] = pe;
pe                859 drivers/gpu/drm/radeon/cik_sdma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                861 drivers/gpu/drm/radeon/cik_sdma.c 		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
pe                892 drivers/gpu/drm/radeon/cik_sdma.c 			   uint64_t pe,
pe                911 drivers/gpu/drm/radeon/cik_sdma.c 		ib->ptr[ib->length_dw++] = pe; /* dst addr */
pe                912 drivers/gpu/drm/radeon/cik_sdma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
pe                921 drivers/gpu/drm/radeon/cik_sdma.c 		pe += ndw * 8;
pe                317 drivers/gpu/drm/radeon/ni_dma.c 			      uint64_t pe, uint64_t src,
pe                329 drivers/gpu/drm/radeon/ni_dma.c 		ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                331 drivers/gpu/drm/radeon/ni_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                334 drivers/gpu/drm/radeon/ni_dma.c 		pe += ndw * 4;
pe                355 drivers/gpu/drm/radeon/ni_dma.c 			       uint64_t pe,
pe                370 drivers/gpu/drm/radeon/ni_dma.c 		ib->ptr[ib->length_dw++] = pe;
pe                371 drivers/gpu/drm/radeon/ni_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                372 drivers/gpu/drm/radeon/ni_dma.c 		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
pe                403 drivers/gpu/drm/radeon/ni_dma.c 			     uint64_t pe,
pe                422 drivers/gpu/drm/radeon/ni_dma.c 		ib->ptr[ib->length_dw++] = pe; /* dst addr */
pe                423 drivers/gpu/drm/radeon/ni_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                431 drivers/gpu/drm/radeon/ni_dma.c 		pe += ndw * 4;
pe               1872 drivers/gpu/drm/radeon/radeon.h 				   uint64_t pe, uint64_t src,
pe               1876 drivers/gpu/drm/radeon/radeon.h 				    uint64_t pe,
pe               1881 drivers/gpu/drm/radeon/radeon.h 				  uint64_t pe,
pe               2711 drivers/gpu/drm/radeon/radeon.h #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
pe               2712 drivers/gpu/drm/radeon/radeon.h #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
pe               2713 drivers/gpu/drm/radeon/radeon.h #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
pe                626 drivers/gpu/drm/radeon/radeon_asic.h 			      uint64_t pe, uint64_t src,
pe                630 drivers/gpu/drm/radeon/radeon_asic.h 			       uint64_t pe,
pe                635 drivers/gpu/drm/radeon/radeon_asic.h 			     uint64_t pe,
pe                732 drivers/gpu/drm/radeon/radeon_asic.h 			  uint64_t pe, uint64_t src,
pe                736 drivers/gpu/drm/radeon/radeon_asic.h 			   uint64_t pe,
pe                741 drivers/gpu/drm/radeon/radeon_asic.h 			 uint64_t pe,
pe                834 drivers/gpu/drm/radeon/radeon_asic.h 			    uint64_t pe, uint64_t src,
pe                838 drivers/gpu/drm/radeon/radeon_asic.h 			     uint64_t pe,
pe                843 drivers/gpu/drm/radeon/radeon_asic.h 			   uint64_t pe,
pe                 84 drivers/gpu/drm/radeon/radeon_trace.h 	    TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
pe                 86 drivers/gpu/drm/radeon/radeon_trace.h 	    TP_ARGS(pe, addr, count, incr, flags),
pe                 88 drivers/gpu/drm/radeon/radeon_trace.h 			     __field(u64, pe)
pe                 96 drivers/gpu/drm/radeon/radeon_trace.h 			   __entry->pe = pe;
pe                103 drivers/gpu/drm/radeon/radeon_trace.h 		      __entry->pe, __entry->addr, __entry->incr,
pe                361 drivers/gpu/drm/radeon/radeon_vm.c 				uint64_t pe,
pe                365 drivers/gpu/drm/radeon/radeon_vm.c 	trace_radeon_vm_set_page(pe, addr, count, incr, flags);
pe                369 drivers/gpu/drm/radeon/radeon_vm.c 		radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
pe                372 drivers/gpu/drm/radeon/radeon_vm.c 		radeon_asic_vm_write_pages(rdev, ib, pe, addr,
pe                376 drivers/gpu/drm/radeon/radeon_vm.c 		radeon_asic_vm_set_pages(rdev, ib, pe, addr,
pe                 71 drivers/gpu/drm/radeon/si_dma.c 			  uint64_t pe, uint64_t src,
pe                 81 drivers/gpu/drm/radeon/si_dma.c 		ib->ptr[ib->length_dw++] = lower_32_bits(pe);
pe                 83 drivers/gpu/drm/radeon/si_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                 86 drivers/gpu/drm/radeon/si_dma.c 		pe += bytes;
pe                107 drivers/gpu/drm/radeon/si_dma.c 			   uint64_t pe,
pe                121 drivers/gpu/drm/radeon/si_dma.c 		ib->ptr[ib->length_dw++] = pe;
pe                122 drivers/gpu/drm/radeon/si_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                123 drivers/gpu/drm/radeon/si_dma.c 		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
pe                154 drivers/gpu/drm/radeon/si_dma.c 			 uint64_t pe,
pe                173 drivers/gpu/drm/radeon/si_dma.c 		ib->ptr[ib->length_dw++] = pe; /* dst addr */
pe                174 drivers/gpu/drm/radeon/si_dma.c 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
pe                181 drivers/gpu/drm/radeon/si_dma.c 		pe += ndw * 4;
pe                471 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c static DEVICE_ATTR_RW(pe);
pe                381 drivers/hwtracing/stm/core.c 	struct stm_pdrv_entry *pe;
pe                389 drivers/hwtracing/stm/core.c 	list_for_each_entry(pe, &stm_pdrv_head, entry) {
pe                390 drivers/hwtracing/stm/core.c 		if (!strcmp(name, pe->pdrv->name))
pe                391 drivers/hwtracing/stm/core.c 			return pe;
pe                399 drivers/hwtracing/stm/core.c 	struct stm_pdrv_entry *pe = NULL;
pe                409 drivers/hwtracing/stm/core.c 	pe = kzalloc(sizeof(*pe), GFP_KERNEL);
pe                410 drivers/hwtracing/stm/core.c 	if (!pe)
pe                414 drivers/hwtracing/stm/core.c 		pe->node_type = get_policy_node_type(pdrv->policy_attr);
pe                415 drivers/hwtracing/stm/core.c 		if (!pe->node_type)
pe                419 drivers/hwtracing/stm/core.c 	list_add_tail(&pe->entry, &stm_pdrv_head);
pe                420 drivers/hwtracing/stm/core.c 	pe->pdrv = pdrv;
pe                427 drivers/hwtracing/stm/core.c 		kfree(pe);
pe                435 drivers/hwtracing/stm/core.c 	struct stm_pdrv_entry *pe, *iter;
pe                439 drivers/hwtracing/stm/core.c 	list_for_each_entry_safe(pe, iter, &stm_pdrv_head, entry) {
pe                440 drivers/hwtracing/stm/core.c 		if (pe->pdrv == pdrv) {
pe                441 drivers/hwtracing/stm/core.c 			list_del(&pe->entry);
pe                443 drivers/hwtracing/stm/core.c 			if (pe->node_type) {
pe                444 drivers/hwtracing/stm/core.c 				kfree(pe->node_type->ct_attrs);
pe                445 drivers/hwtracing/stm/core.c 				kfree(pe->node_type);
pe                447 drivers/hwtracing/stm/core.c 			kfree(pe);
pe                470 drivers/hwtracing/stm/core.c 	const struct stm_pdrv_entry *pe;
pe                474 drivers/hwtracing/stm/core.c 	pe = __stm_lookup_protocol(name);
pe                475 drivers/hwtracing/stm/core.c 	if (pe && pe->pdrv && stm_get_protocol(pe->pdrv)) {
pe                476 drivers/hwtracing/stm/core.c 		*pdrv = pe->pdrv;
pe                477 drivers/hwtracing/stm/core.c 		*node_type = pe->node_type;
pe                482 drivers/hwtracing/stm/core.c 	return pe ? 0 : -ENOENT;
pe                262 drivers/iommu/intel-pasid.c static inline void pasid_clear_entry(struct pasid_entry *pe)
pe                264 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[0], 0);
pe                265 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[1], 0);
pe                266 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[2], 0);
pe                267 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[3], 0);
pe                268 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[4], 0);
pe                269 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[5], 0);
pe                270 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[6], 0);
pe                271 drivers/iommu/intel-pasid.c 	WRITE_ONCE(pe->val[7], 0);
pe                276 drivers/iommu/intel-pasid.c 	struct pasid_entry *pe;
pe                278 drivers/iommu/intel-pasid.c 	pe = intel_pasid_get_entry(dev, pasid);
pe                279 drivers/iommu/intel-pasid.c 	if (WARN_ON(!pe))
pe                282 drivers/iommu/intel-pasid.c 	pasid_clear_entry(pe);
pe                298 drivers/iommu/intel-pasid.c pasid_set_domain_id(struct pasid_entry *pe, u64 value)
pe                300 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);
pe                307 drivers/iommu/intel-pasid.c pasid_get_domain_id(struct pasid_entry *pe)
pe                309 drivers/iommu/intel-pasid.c 	return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));
pe                317 drivers/iommu/intel-pasid.c pasid_set_slptr(struct pasid_entry *pe, u64 value)
pe                319 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);
pe                327 drivers/iommu/intel-pasid.c pasid_set_address_width(struct pasid_entry *pe, u64 value)
pe                329 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);
pe                337 drivers/iommu/intel-pasid.c pasid_set_translation_type(struct pasid_entry *pe, u64 value)
pe                339 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);
pe                346 drivers/iommu/intel-pasid.c static inline void pasid_set_fault_enable(struct pasid_entry *pe)
pe                348 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[0], 1 << 1, 0);
pe                355 drivers/iommu/intel-pasid.c static inline void pasid_set_sre(struct pasid_entry *pe)
pe                357 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[2], 1 << 0, 1);
pe                364 drivers/iommu/intel-pasid.c static inline void pasid_set_present(struct pasid_entry *pe)
pe                366 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[0], 1 << 0, 1);
pe                373 drivers/iommu/intel-pasid.c static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
pe                375 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[1], 1 << 23, value << 23);
pe                383 drivers/iommu/intel-pasid.c pasid_set_flptr(struct pasid_entry *pe, u64 value)
pe                385 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);
pe                393 drivers/iommu/intel-pasid.c pasid_set_flpm(struct pasid_entry *pe, u64 value)
pe                395 drivers/iommu/intel-pasid.c 	pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
pe                738 drivers/md/dm-snap.c 	struct dm_snap_pending_exception *pe = mempool_alloc(&s->pending_pool,
pe                742 drivers/md/dm-snap.c 	pe->snap = s;
pe                744 drivers/md/dm-snap.c 	return pe;
pe                747 drivers/md/dm-snap.c static void free_pending_exception(struct dm_snap_pending_exception *pe)
pe                749 drivers/md/dm-snap.c 	struct dm_snapshot *s = pe->snap;
pe                751 drivers/md/dm-snap.c 	mempool_free(pe, &s->pending_pool);
pe               1638 drivers/md/dm-snap.c 	struct dm_snap_pending_exception *pe = context;
pe               1640 drivers/md/dm-snap.c 	struct dm_snapshot *s = pe->snap;
pe               1647 drivers/md/dm-snap.c 	dm_exception_table_lock_init(s, pe->e.old_chunk, &lock);
pe               1666 drivers/md/dm-snap.c 	*e = pe->e;
pe               1689 drivers/md/dm-snap.c 	if (__chunk_is_tracked(s, pe->e.old_chunk)) {
pe               1691 drivers/md/dm-snap.c 		__check_for_conflicting_io(s, pe->e.old_chunk);
pe               1697 drivers/md/dm-snap.c 	dm_remove_exception(&pe->e);
pe               1701 drivers/md/dm-snap.c 	snapshot_bios = bio_list_get(&pe->snapshot_bios);
pe               1702 drivers/md/dm-snap.c 	origin_bios = bio_list_get(&pe->origin_bios);
pe               1703 drivers/md/dm-snap.c 	full_bio = pe->full_bio;
pe               1705 drivers/md/dm-snap.c 		full_bio->bi_end_io = pe->full_bio_end_io;
pe               1721 drivers/md/dm-snap.c 	free_pending_exception(pe);
pe               1724 drivers/md/dm-snap.c static void complete_exception(struct dm_snap_pending_exception *pe)
pe               1726 drivers/md/dm-snap.c 	struct dm_snapshot *s = pe->snap;
pe               1729 drivers/md/dm-snap.c 	s->store->type->commit_exception(s->store, &pe->e, !pe->copy_error,
pe               1730 drivers/md/dm-snap.c 					 pending_complete, pe);
pe               1739 drivers/md/dm-snap.c 	struct dm_snap_pending_exception *pe = context;
pe               1740 drivers/md/dm-snap.c 	struct dm_snapshot *s = pe->snap;
pe               1742 drivers/md/dm-snap.c 	pe->copy_error = read_err || write_err;
pe               1744 drivers/md/dm-snap.c 	if (pe->exception_sequence == s->exception_complete_sequence) {
pe               1748 drivers/md/dm-snap.c 		complete_exception(pe);
pe               1752 drivers/md/dm-snap.c 			pe = rb_entry(next, struct dm_snap_pending_exception,
pe               1754 drivers/md/dm-snap.c 			if (pe->exception_sequence != s->exception_complete_sequence)
pe               1758 drivers/md/dm-snap.c 			rb_erase(&pe->out_of_order_node, &s->out_of_order_tree);
pe               1759 drivers/md/dm-snap.c 			complete_exception(pe);
pe               1771 drivers/md/dm-snap.c 			BUG_ON(pe->exception_sequence == pe2->exception_sequence);
pe               1772 drivers/md/dm-snap.c 			if (pe->exception_sequence < pe2->exception_sequence)
pe               1778 drivers/md/dm-snap.c 		rb_link_node(&pe->out_of_order_node, parent, p);
pe               1779 drivers/md/dm-snap.c 		rb_insert_color(&pe->out_of_order_node, &s->out_of_order_tree);
pe               1787 drivers/md/dm-snap.c static void start_copy(struct dm_snap_pending_exception *pe)
pe               1789 drivers/md/dm-snap.c 	struct dm_snapshot *s = pe->snap;
pe               1797 drivers/md/dm-snap.c 	src.sector = chunk_to_sector(s->store, pe->e.old_chunk);
pe               1801 drivers/md/dm-snap.c 	dest.sector = chunk_to_sector(s->store, pe->e.new_chunk);
pe               1806 drivers/md/dm-snap.c 	dm_kcopyd_copy(s->kcopyd_client, &src, 1, &dest, 0, copy_callback, pe);
pe               1816 drivers/md/dm-snap.c static void start_full_bio(struct dm_snap_pending_exception *pe,
pe               1819 drivers/md/dm-snap.c 	struct dm_snapshot *s = pe->snap;
pe               1822 drivers/md/dm-snap.c 	pe->full_bio = bio;
pe               1823 drivers/md/dm-snap.c 	pe->full_bio_end_io = bio->bi_end_io;
pe               1827 drivers/md/dm-snap.c 						   copy_callback, pe);
pe               1854 drivers/md/dm-snap.c 			   struct dm_snap_pending_exception *pe, chunk_t chunk)
pe               1856 drivers/md/dm-snap.c 	pe->e.old_chunk = chunk;
pe               1857 drivers/md/dm-snap.c 	bio_list_init(&pe->origin_bios);
pe               1858 drivers/md/dm-snap.c 	bio_list_init(&pe->snapshot_bios);
pe               1859 drivers/md/dm-snap.c 	pe->started = 0;
pe               1860 drivers/md/dm-snap.c 	pe->full_bio = NULL;
pe               1863 drivers/md/dm-snap.c 	if (s->store->type->prepare_exception(s->store, &pe->e)) {
pe               1865 drivers/md/dm-snap.c 		free_pending_exception(pe);
pe               1869 drivers/md/dm-snap.c 	pe->exception_sequence = s->exception_start_sequence++;
pe               1872 drivers/md/dm-snap.c 	dm_insert_exception(&s->pending, &pe->e);
pe               1874 drivers/md/dm-snap.c 	return pe;
pe               1887 drivers/md/dm-snap.c 			 struct dm_snap_pending_exception *pe, chunk_t chunk)
pe               1893 drivers/md/dm-snap.c 		free_pending_exception(pe);
pe               1897 drivers/md/dm-snap.c 	return __insert_pending_exception(s, pe, chunk);
pe               1947 drivers/md/dm-snap.c 	struct dm_snap_pending_exception *pe = NULL;
pe               2025 drivers/md/dm-snap.c 		pe = __lookup_pending_exception(s, chunk);
pe               2026 drivers/md/dm-snap.c 		if (!pe) {
pe               2028 drivers/md/dm-snap.c 			pe = alloc_pending_exception(s);
pe               2033 drivers/md/dm-snap.c 				free_pending_exception(pe);
pe               2038 drivers/md/dm-snap.c 			pe = __find_pending_exception(s, pe, chunk);
pe               2039 drivers/md/dm-snap.c 			if (!pe) {
pe               2059 drivers/md/dm-snap.c 		remap_exception(s, &pe->e, bio, chunk);
pe               2063 drivers/md/dm-snap.c 		if (!pe->started && io_overlaps_chunk(s, bio)) {
pe               2064 drivers/md/dm-snap.c 			pe->started = 1;
pe               2069 drivers/md/dm-snap.c 			start_full_bio(pe, bio);
pe               2073 drivers/md/dm-snap.c 		bio_list_add(&pe->snapshot_bios, bio);
pe               2075 drivers/md/dm-snap.c 		if (!pe->started) {
pe               2077 drivers/md/dm-snap.c 			pe->started = 1;
pe               2082 drivers/md/dm-snap.c 			start_copy(pe);
pe               2425 drivers/md/dm-snap.c 	struct dm_snap_pending_exception *pe, *pe2;
pe               2458 drivers/md/dm-snap.c 		pe = __lookup_pending_exception(snap, chunk);
pe               2459 drivers/md/dm-snap.c 		if (!pe) {
pe               2470 drivers/md/dm-snap.c 			pe = alloc_pending_exception(snap);
pe               2478 drivers/md/dm-snap.c 					free_pending_exception(pe);
pe               2482 drivers/md/dm-snap.c 				pe = __insert_pending_exception(snap, pe, chunk);
pe               2483 drivers/md/dm-snap.c 				if (!pe) {
pe               2491 drivers/md/dm-snap.c 				free_pending_exception(pe);
pe               2492 drivers/md/dm-snap.c 				pe = pe2;
pe               2504 drivers/md/dm-snap.c 			bio_list_add(&pe->origin_bios, bio);
pe               2507 drivers/md/dm-snap.c 			if (!pe->started) {
pe               2508 drivers/md/dm-snap.c 				pe->started = 1;
pe               2509 drivers/md/dm-snap.c 				pe_to_start_last = pe;
pe               2513 drivers/md/dm-snap.c 		if (!pe->started) {
pe               2514 drivers/md/dm-snap.c 			pe->started = 1;
pe               2515 drivers/md/dm-snap.c 			pe_to_start_now = pe;
pe                271 drivers/misc/cxl/api.c 	pr_devel("%s: pe: %i\n", __func__, ctx->pe);
pe                420 drivers/misc/cxl/api.c 	name = kasprintf(GFP_KERNEL, "cxl:%d", ctx->pe);
pe                101 drivers/misc/cxl/context.c 	ctx->pe = i;
pe                104 drivers/misc/cxl/context.c 		ctx->external_pe = ctx->pe;
pe                136 drivers/misc/cxl/context.c 			__func__, ctx->pe, vmf->address, offset);
pe                221 drivers/misc/cxl/context.c 		 ctx->psn_phys, ctx->pe , ctx->master);
pe                347 drivers/misc/cxl/context.c 	idr_remove(&ctx->afu->contexts_idr, ctx->pe);
pe                600 drivers/misc/cxl/cxl.h 	int pe;
pe                117 drivers/misc/cxl/fault.c 	pr_devel("CXL interrupt: Segment fault pe: %i ea: %#llx\n", ctx->pe, ea);
pe                189 drivers/misc/cxl/fault.c 		pr_devel("Page fault successfully handled for pe: %i!\n", ctx->pe);
pe                239 drivers/misc/cxl/fault.c 		    cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) != ctx->pe) {
pe                256 drivers/misc/cxl/fault.c 		"DSISR: %#llx DAR: %#llx\n", ctx->pe, dsisr, dar);
pe                263 drivers/misc/cxl/fault.c 				 __func__, ctx->pe, pid_nr(ctx->pid));
pe                268 drivers/misc/cxl/fault.c 				 ctx->pe, pid_nr(ctx->pid));
pe                 93 drivers/misc/cxl/file.c 	pr_devel("afu_open pe: %i\n", ctx->pe);
pe                122 drivers/misc/cxl/file.c 		 __func__, ctx->pe);
pe                154 drivers/misc/cxl/file.c 	pr_devel("%s: pe: %i\n", __func__, ctx->pe);
pe                283 drivers/misc/cxl/file.c 	pr_devel("%s: pe: %i\n", __func__, ctx->pe);
pe                373 drivers/misc/cxl/file.c 	pr_devel("afu_poll wait done pe: %i\n", ctx->pe);
pe                384 drivers/misc/cxl/file.c 	pr_devel("afu_poll pe: %i returning %#x\n", ctx->pe, mask);
pe                472 drivers/misc/cxl/file.c 	event.header.process_element = ctx->pe;
pe                161 drivers/misc/cxl/guest.c 	pr_devel("%d: received PSL interrupt %i\n", ctx->pe, irq);
pe                610 drivers/misc/cxl/guest.c 			ctx->pe, ctx->external_pe, ctx->psn_size);
pe                 42 drivers/misc/cxl/irq.c 	pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
pe                 45 drivers/misc/cxl/irq.c 		pr_devel("CXL interrupt: Scheduling translation fault handling for later (pe: %i)\n", ctx->pe);
pe                 64 drivers/misc/cxl/irq.c 					    ctx->pe, irq_info->afu_err);
pe                 93 drivers/misc/cxl/irq.c 	pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
pe                106 drivers/misc/cxl/irq.c 		pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe);
pe                127 drivers/misc/cxl/irq.c 		pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe);
pe                150 drivers/misc/cxl/irq.c 					    ctx->pe, irq_info->afu_err);
pe                201 drivers/misc/cxl/irq.c 		     ctx->pe, irq, hwirq);
pe                207 drivers/misc/cxl/irq.c 	       afu_irq, ctx->pe, irq, hwirq);
pe                338 drivers/misc/cxl/irq.c 						   ctx->pe, j);
pe                 65 drivers/misc/cxl/main.c 		 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
pe                443 drivers/misc/cxl/native.c 	*(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
pe                445 drivers/misc/cxl/native.c 	cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
pe                464 drivers/misc/cxl/native.c 		    (cmd | (cmd >> 16) | ctx->pe))
pe                486 drivers/misc/cxl/native.c 	pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
pe                489 drivers/misc/cxl/native.c 	pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
pe                503 drivers/misc/cxl/native.c 	pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
pe                512 drivers/misc/cxl/native.c 	pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
pe                522 drivers/misc/cxl/native.c 	pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
pe                534 drivers/misc/cxl/native.c 	pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
pe                547 drivers/misc/cxl/native.c 			(ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
pe                678 drivers/misc/cxl/native.c 				__func__, ctx->pe, pid_nr(ctx->pid));
pe               1228 drivers/misc/cxl/native.c 		if (ph != ctx->pe)
pe                 71 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                 77 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                 83 drivers/misc/cxl/trace.h 		__entry->pe
pe                 96 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                106 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                117 drivers/misc/cxl/trace.h 		__entry->pe,
pe                137 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                146 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                155 drivers/misc/cxl/trace.h 		__entry->pe,
pe                170 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                179 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                188 drivers/misc/cxl/trace.h 		__entry->pe,
pe                204 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                213 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                222 drivers/misc/cxl/trace.h 		__entry->pe,
pe                237 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                244 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                251 drivers/misc/cxl/trace.h 		__entry->pe,
pe                264 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                271 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                278 drivers/misc/cxl/trace.h 		__entry->pe,
pe                291 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                300 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                309 drivers/misc/cxl/trace.h 		__entry->pe,
pe                324 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                332 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                340 drivers/misc/cxl/trace.h 		__entry->pe,
pe                354 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                361 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                368 drivers/misc/cxl/trace.h 		__entry->pe,
pe                381 drivers/misc/cxl/trace.h 		__field(u16, pe)
pe                389 drivers/misc/cxl/trace.h 		__entry->pe = ctx->pe;
pe                397 drivers/misc/cxl/trace.h 		__entry->pe,
pe                 64 drivers/misc/ocxl/link.c 		u64 pe;
pe                 99 drivers/misc/ocxl/link.c static void read_irq(struct spa *spa, u64 *dsisr, u64 *dar, u64 *pe)
pe                106 drivers/misc/ocxl/link.c 	*pe = reg & SPA_PE_MASK;
pe                122 drivers/misc/ocxl/link.c 		trace_ocxl_fault_ack(spa->spa_mem, spa->xsl_fault.pe,
pe                186 drivers/misc/ocxl/link.c 	struct ocxl_process_element *pe;
pe                194 drivers/misc/ocxl/link.c 	pe = spa->spa_mem + pe_handle;
pe                195 drivers/misc/ocxl/link.c 	pid = be32_to_cpu(pe->pid);
pe                241 drivers/misc/ocxl/link.c 			spa->xsl_fault.pe = pe_handle;
pe                502 drivers/misc/ocxl/link.c 	struct ocxl_process_element *pe;
pe                512 drivers/misc/ocxl/link.c 	pe = spa->spa_mem + pe_handle;
pe                514 drivers/misc/ocxl/link.c 	if (pe->software_state) {
pe                529 drivers/misc/ocxl/link.c 	memset(pe, 0, sizeof(struct ocxl_process_element));
pe                530 drivers/misc/ocxl/link.c 	pe->config_state = cpu_to_be64(calculate_cfg_state(pidr == 0));
pe                531 drivers/misc/ocxl/link.c 	pe->lpid = cpu_to_be32(mfspr(SPRN_LPID));
pe                532 drivers/misc/ocxl/link.c 	pe->pid = cpu_to_be32(pidr);
pe                533 drivers/misc/ocxl/link.c 	pe->tid = cpu_to_be32(tidr);
pe                534 drivers/misc/ocxl/link.c 	pe->amr = cpu_to_be64(amr);
pe                535 drivers/misc/ocxl/link.c 	pe->software_state = cpu_to_be32(SPA_PE_VALID);
pe                579 drivers/misc/ocxl/link.c 	struct ocxl_process_element *pe;
pe                586 drivers/misc/ocxl/link.c 	pe = spa->spa_mem + pe_handle;
pe                590 drivers/misc/ocxl/link.c 	pe->tid = cpu_to_be32(tid);
pe                615 drivers/misc/ocxl/link.c 	struct ocxl_process_element *pe;
pe                641 drivers/misc/ocxl/link.c 	pe = spa->spa_mem + pe_handle;
pe                645 drivers/misc/ocxl/link.c 	if (!(be32_to_cpu(pe->software_state) & SPA_PE_VALID)) {
pe                651 drivers/misc/ocxl/link.c 				be32_to_cpu(pe->pid), be32_to_cpu(pe->tid));
pe                653 drivers/misc/ocxl/link.c 	memset(pe, 0, sizeof(struct ocxl_process_element));
pe                 71 drivers/misc/ocxl/trace.h 	TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),
pe                 72 drivers/misc/ocxl/trace.h 	TP_ARGS(spa, pe, dsisr, dar, tfc),
pe                 76 drivers/misc/ocxl/trace.h 		__field(u64, pe)
pe                 84 drivers/misc/ocxl/trace.h 		__entry->pe = pe;
pe                 92 drivers/misc/ocxl/trace.h 		__entry->pe,
pe                100 drivers/misc/ocxl/trace.h 	TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),
pe                101 drivers/misc/ocxl/trace.h 	TP_ARGS(spa, pe, dsisr, dar, tfc)
pe                105 drivers/misc/ocxl/trace.h 	TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),
pe                106 drivers/misc/ocxl/trace.h 	TP_ARGS(spa, pe, dsisr, dar, tfc)
pe                248 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                255 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                257 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe                265 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]);
pe                266 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]);
pe                282 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                287 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		mvpp2_prs_init_from_hw(port->priv, &pe, i);
pe                289 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe                303 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                316 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                318 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe                326 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 			mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
pe                352 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                355 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);
pe                357 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe                370 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                373 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);
pe                375 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	ai = pe.tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK;
pe                376 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	ai_mask = (pe.tcam[MVPP2_PRS_TCAM_AI_WORD] >> 16) & MVPP2_PRS_AI_MASK;
pe                388 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                392 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);
pe                395 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 		mvpp2_prs_tcam_data_byte_get(&pe, i, &data[i], &mask[i]);
pe                407 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	struct mvpp2_prs_entry pe;
pe                409 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);
pe                411 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	seq_printf(s, "%*phN\n", 14, pe.sram);
pe                 22 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
pe                 26 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
pe                 30 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
pe                 33 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
pe                 35 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]);
pe                 38 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
pe                 40 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]);
pe                 46 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
pe                 54 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(pe, 0, sizeof(*pe));
pe                 55 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->index = tid;
pe                 58 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
pe                 60 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
pe                 62 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
pe                 66 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
pe                 69 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
pe                 71 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
pe                101 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
pe                103 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK);
pe                104 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);
pe                105 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK);
pe                106 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);
pe                110 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
pe                114 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port));
pe                116 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port));
pe                120 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
pe                123 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK);
pe                124 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK);
pe                125 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK);
pe                129 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
pe                131 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK;
pe                135 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
pe                141 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos);
pe                142 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos);
pe                143 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos;
pe                144 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos);
pe                148 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
pe                154 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	*byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff;
pe                155 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	*enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff;
pe                159 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,
pe                164 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff;
pe                169 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,
pe                179 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i);
pe                181 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i);
pe                184 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable);
pe                188 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)
pe                190 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK;
pe                194 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
pe                197 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
pe                198 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
pe                202 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset,
pe                205 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf);
pe                206 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff);
pe                210 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
pe                213 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num)));
pe                217 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
pe                220 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num)));
pe                224 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
pe                234 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i,
pe                237 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_bits_clear(pe,
pe                241 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
pe                246 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)
pe                248 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	return pe->sram[MVPP2_PRS_SRAM_RI_WORD];
pe                252 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
pe                262 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i,
pe                265 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_bits_clear(pe,
pe                269 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
pe                274 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
pe                281 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	bits = (pe->sram[ai_off] >> ai_shift) |
pe                282 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	       (pe->sram[ai_off + 1] << (32 - ai_shift));
pe                290 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
pe                295 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, sram_next_off,
pe                297 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
pe                303 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
pe                308 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
pe                311 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
pe                315 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |=
pe                319 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
pe                321 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
pe                324 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
pe                330 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
pe                336 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
pe                339 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
pe                343 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
pe                345 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS,
pe                349 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
pe                351 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
pe                354 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
pe                356 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
pe                360 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
pe                366 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                377 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                378 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		bits = mvpp2_prs_sram_ai_get(&pe);
pe                411 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                415 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL);
pe                418 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe                419 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
pe                420 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = MVPP2_PE_DROP_ALL;
pe                423 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
pe                426 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe                427 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe                430 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
pe                433 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, 0);
pe                437 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port, add);
pe                439 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                446 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                463 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                465 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe                466 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
pe                467 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe                470 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
pe                473 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK);
pe                476 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match,
pe                480 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
pe                484 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, 0);
pe                487 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
pe                491 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port, add);
pe                493 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                500 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                513 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                516 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe                517 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
pe                518 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe                521 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
pe                525 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_tcam_data_byte_set(&pe, 0,
pe                531 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 				mvpp2_prs_sram_ai_update(&pe, 1,
pe                534 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 				mvpp2_prs_sram_ai_update(&pe, 0,
pe                538 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,
pe                541 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
pe                544 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_shift_set(&pe, shift,
pe                548 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
pe                550 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe                554 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, 0);
pe                558 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port, add);
pe                560 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                567 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                584 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                587 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe                588 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
pe                589 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe                592 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);
pe                593 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_match_etype(&pe, 2, 0);
pe                595 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,
pe                598 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
pe                602 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
pe                606 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_tcam_data_byte_set(&pe,
pe                611 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_ai_update(&pe, 0,
pe                614 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe                617 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
pe                619 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe                622 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, port_mask);
pe                626 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port, add);
pe                628 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                634 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                647 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                648 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid);
pe                653 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		ri_bits = mvpp2_prs_sram_ri_get(&pe);
pe                657 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		ai_bits = mvpp2_prs_tcam_ai_get(&pe);
pe                676 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                680 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe                700 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_init_from_hw(priv, &pe, tid_aux);
pe                701 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			ri_bits = mvpp2_prs_sram_ri_get(&pe);
pe                710 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe                711 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe                712 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe                714 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_match_etype(&pe, 0, tpid);
pe                717 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
pe                720 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe                723 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,
pe                727 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE,
pe                730 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK);
pe                732 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
pe                734 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                737 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, port_map);
pe                739 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                761 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                774 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                776 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) &&
pe                777 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2);
pe                782 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK;
pe                796 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                798 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe                823 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_init_from_hw(priv, &pe, tid_aux);
pe                824 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			ri_bits = mvpp2_prs_sram_ri_get(&pe);
pe                834 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe                835 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe                836 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe                840 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_match_etype(&pe, 0, tpid1);
pe                841 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_match_etype(&pe, 4, tpid2);
pe                843 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe                845 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
pe                847 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
pe                849 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,
pe                852 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
pe                854 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe                858 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, port_map);
pe                859 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                868 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                881 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe                882 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe                883 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe                886 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe                887 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe                889 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
pe                892 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
pe                894 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
pe                896 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00,
pe                898 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00,
pe                901 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
pe                902 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
pe                904 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe                907 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe                908 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                916 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe                918 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
pe                919 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
pe                920 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
pe                922 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE,
pe                925 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0);
pe                926 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0);
pe                929 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe                930 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                938 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe                946 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe                947 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe                948 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe                952 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,
pe                954 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
pe                959 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);
pe                960 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);
pe                961 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);
pe                962 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);
pe                963 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,
pe                971 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe                972 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe                974 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
pe                977 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe                980 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe                981 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe                990 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1002 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1003 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1004 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1007 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1008 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1009 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
pe               1010 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
pe               1014 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);
pe               1015 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
pe               1018 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1021 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
pe               1022 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1030 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1041 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1042 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1043 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1046 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1047 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
pe               1049 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
pe               1052 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe               1054 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,
pe               1056 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
pe               1058 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1061 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
pe               1062 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1097 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1101 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		memset(&pe, 0, sizeof(pe));
pe               1102 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1103 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
pe               1106 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, 0);
pe               1109 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
pe               1110 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
pe               1113 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
pe               1114 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_hw_write(priv, &pe);
pe               1121 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1123 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1125 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_MH_DEFAULT;
pe               1126 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
pe               1127 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
pe               1129 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
pe               1132 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1135 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
pe               1136 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1144 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1146 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1149 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
pe               1150 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
pe               1152 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
pe               1154 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1155 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1158 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1161 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
pe               1162 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1173 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1206 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1207 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
pe               1208 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_DSA_DEFAULT;
pe               1209 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe               1212 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe               1213 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
pe               1216 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe               1219 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1221 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1227 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1229 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1232 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_VID_FLTR_DEFAULT;
pe               1233 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
pe               1235 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT);
pe               1238 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
pe               1242 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe               1244 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1247 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1250 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
pe               1251 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1254 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1257 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT;
pe               1258 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
pe               1260 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT,
pe               1264 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN,
pe               1268 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe               1270 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1273 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1276 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
pe               1277 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1283 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1292 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1293 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1294 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1296 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);
pe               1298 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
pe               1300 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
pe               1301 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
pe               1305 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1306 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1307 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = false;
pe               1308 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
pe               1310 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1318 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1319 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1320 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1322 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);
pe               1325 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1326 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1327 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
pe               1330 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1335 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1336 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1337 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = true;
pe               1338 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
pe               1340 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1348 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1349 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1350 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1352 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
pe               1355 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1356 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1357 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
pe               1362 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1367 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1368 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1369 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = true;
pe               1370 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
pe               1374 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1382 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1383 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1384 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1386 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);
pe               1387 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
pe               1392 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe               1393 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
pe               1396 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
pe               1399 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1404 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1405 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1406 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = false;
pe               1407 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
pe               1409 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1417 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1419 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
pe               1424 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
pe               1425 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
pe               1426 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
pe               1430 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1431 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1432 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = false;
pe               1433 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
pe               1435 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1443 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1444 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1445 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1447 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);
pe               1450 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
pe               1453 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1454 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
pe               1457 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1461 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1462 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1463 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = false;
pe               1464 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
pe               1466 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1469 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
pe               1470 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1471 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_ETH_TYPE_UN;
pe               1474 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1477 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1478 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1479 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
pe               1482 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1487 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
pe               1488 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
pe               1489 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].finish = true;
pe               1490 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
pe               1492 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1506 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1540 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1541 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe               1542 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_VLAN_DBL;
pe               1544 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
pe               1547 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe               1548 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
pe               1551 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,
pe               1554 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1557 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
pe               1558 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1561 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1562 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
pe               1563 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_VLAN_NONE;
pe               1565 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1566 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
pe               1570 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1573 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
pe               1574 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1582 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1591 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1592 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
pe               1593 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1595 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, PPP_IP);
pe               1597 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe               1598 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
pe               1601 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
pe               1604 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1609 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
pe               1610 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1618 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1620 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
pe               1626 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
pe               1627 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
pe               1628 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
pe               1632 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
pe               1633 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1641 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1642 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
pe               1643 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1645 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);
pe               1647 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1648 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
pe               1651 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
pe               1654 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1659 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
pe               1660 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1668 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1669 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
pe               1670 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1672 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
pe               1676 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1677 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1679 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
pe               1684 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
pe               1685 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1693 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1726 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1727 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe               1728 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_IP4_PROTO_UN;
pe               1731 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe               1732 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe               1734 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
pe               1737 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
pe               1739 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
pe               1742 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
pe               1744 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1747 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe               1748 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1751 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1752 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
pe               1753 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_IP4_ADDR_UN;
pe               1756 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1757 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1758 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
pe               1761 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
pe               1764 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1767 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe               1768 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1776 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1819 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1820 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1821 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               1824 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1825 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1826 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |
pe               1831 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
pe               1832 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
pe               1836 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe               1837 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1840 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1841 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1842 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_IP6_PROTO_UN;
pe               1845 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1846 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1847 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
pe               1850 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
pe               1854 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
pe               1857 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1860 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe               1861 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1864 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
pe               1865 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1866 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;
pe               1869 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               1870 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
pe               1871 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
pe               1874 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,
pe               1877 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1880 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
pe               1881 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1884 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
pe               1885 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1886 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = MVPP2_PE_IP6_ADDR_UN;
pe               1889 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
pe               1890 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
pe               1892 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
pe               1895 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe               1897 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
pe               1899 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               1902 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
pe               1903 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               1912 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1923 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(port->priv, &pe, tid);
pe               1925 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]);
pe               1926 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]);
pe               1947 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               1950 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               1973 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
pe               1974 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe               1977 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, 0);
pe               1979 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe               1983 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port->id, true);
pe               1986 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               1989 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe               1992 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid);
pe               1995 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe               1998 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
pe               1999 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               2054 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               2059 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               2061 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               2069 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
pe               2072 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, 0);
pe               2075 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port->id, true);
pe               2078 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
pe               2081 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
pe               2084 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
pe               2088 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
pe               2091 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
pe               2092 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               2163 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
pe               2170 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
pe               2186 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               2199 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe               2200 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		entry_pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe               2202 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		if (mvpp2_prs_mac_range_equals(&pe, da, mask) &&
pe               2216 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               2219 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               2238 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe               2241 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_port_map_set(&pe, 0);
pe               2243 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe               2246 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
pe               2249 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_set(&pe, port->id, add);
pe               2252 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe               2257 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_hw_inv(priv, pe.index);
pe               2258 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		priv->prs_shadow[pe.index].valid = false;
pe               2263 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
pe               2268 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);
pe               2282 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
pe               2284 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
pe               2288 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
pe               2292 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF;
pe               2293 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
pe               2294 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               2323 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               2336 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(priv, &pe, tid);
pe               2338 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pmap = mvpp2_prs_tcam_port_map_get(&pe);
pe               2346 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
pe               2413 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               2417 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               2425 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	pe.index = tid;
pe               2430 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK);
pe               2431 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
pe               2434 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i],
pe               2438 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
pe               2439 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               2440 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
pe               2441 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(priv, &pe);
pe               2449 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	struct mvpp2_prs_entry pe;
pe               2452 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	memset(&pe, 0, sizeof(pe));
pe               2465 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		pe.index = tid;
pe               2468 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
pe               2469 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
pe               2472 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS);
pe               2474 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_prs_init_from_hw(port->priv, &pe, tid);
pe               2477 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
pe               2478 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id));
pe               2479 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_hw_write(port->priv, &pe);
pe                297 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
pe                300 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe);
pe                302 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
pe               3957 drivers/net/wireless/ath/ath10k/wmi.c 	struct pulse_event pe;
pe               4015 drivers/net/wireless/ath/ath10k/wmi.c 	pe.ts = tsf64;
pe               4016 drivers/net/wireless/ath/ath10k/wmi.c 	pe.freq = ch->center_freq;
pe               4017 drivers/net/wireless/ath/ath10k/wmi.c 	pe.width = width;
pe               4018 drivers/net/wireless/ath/ath10k/wmi.c 	pe.rssi = rssi;
pe               4019 drivers/net/wireless/ath/ath10k/wmi.c 	pe.chirp = (MS(reg0, RADAR_REPORT_REG0_PULSE_IS_CHIRP) != 0);
pe               4022 drivers/net/wireless/ath/ath10k/wmi.c 		   pe.freq, pe.width, pe.rssi, pe.ts);
pe               4026 drivers/net/wireless/ath/ath10k/wmi.c 	if (!ar->dfs_detector->add_pulse(ar->dfs_detector, &pe, &rs)) {
pe                202 drivers/net/wireless/ath/ath9k/dfs.c 			      struct pulse_event *pe)
pe                266 drivers/net/wireless/ath/ath9k/dfs.c 	pe->width = dur_to_usecs(sc->sc_ah, dur);
pe                267 drivers/net/wireless/ath/ath9k/dfs.c 	pe->rssi = rssi;
pe                274 drivers/net/wireless/ath/ath9k/dfs.c ath9k_dfs_process_radar_pulse(struct ath_softc *sc, struct pulse_event *pe)
pe                280 drivers/net/wireless/ath/ath9k/dfs.c 	if (!pd->add_pulse(pd, pe, NULL))
pe                295 drivers/net/wireless/ath/ath9k/dfs.c 	struct pulse_event pe;
pe                331 drivers/net/wireless/ath/ath9k/dfs.c 	pe.freq = ah->curchan->channel;
pe                332 drivers/net/wireless/ath/ath9k/dfs.c 	pe.ts = mactime;
pe                333 drivers/net/wireless/ath/ath9k/dfs.c 	if (!ath9k_postprocess_radar_event(sc, &ard, &pe))
pe                336 drivers/net/wireless/ath/ath9k/dfs.c 	if (pe.width > MIN_CHIRP_PULSE_WIDTH &&
pe                337 drivers/net/wireless/ath/ath9k/dfs.c 	    pe.width < MAX_CHIRP_PULSE_WIDTH) {
pe                341 drivers/net/wireless/ath/ath9k/dfs.c 		pe.chirp = ath9k_check_chirping(sc, data, clen, is_ctl, is_ext);
pe                343 drivers/net/wireless/ath/ath9k/dfs.c 		pe.chirp = false;
pe                349 drivers/net/wireless/ath/ath9k/dfs.c 		ard.pulse_bw_info, pe.freq, pe.ts, pe.width, pe.rssi,
pe                350 drivers/net/wireless/ath/ath9k/dfs.c 		pe.ts - sc->dfs_prev_pulse_ts);
pe                351 drivers/net/wireless/ath/ath9k/dfs.c 	sc->dfs_prev_pulse_ts = pe.ts;
pe                353 drivers/net/wireless/ath/ath9k/dfs.c 		ath9k_dfs_process_radar_pulse(sc, &pe);
pe                356 drivers/net/wireless/ath/ath9k/dfs.c 		pe.freq += IS_CHAN_HT40PLUS(ah->curchan) ? 20 : -20;
pe                357 drivers/net/wireless/ath/ath9k/dfs.c 		ath9k_dfs_process_radar_pulse(sc, &pe);
pe                100 drivers/net/wireless/ath/dfs_pattern_detector.h 			  struct pulse_event *pe,
pe                119 drivers/net/wireless/ath/dfs_pri_detector.c static void pool_put_pulse_elem(struct pulse_elem *pe)
pe                122 drivers/net/wireless/ath/dfs_pri_detector.c 	list_add(&pe->head, &pulse_pool);
pe                150 drivers/net/wireless/ath/dfs_pri_detector.c 	struct pulse_elem *pe = NULL;
pe                153 drivers/net/wireless/ath/dfs_pri_detector.c 		pe = list_first_entry(&pulse_pool, struct pulse_elem, head);
pe                154 drivers/net/wireless/ath/dfs_pri_detector.c 		list_del(&pe->head);
pe                158 drivers/net/wireless/ath/dfs_pri_detector.c 	return pe;
pe                 99 drivers/nvme/target/fc.c 	struct nvmet_fc_port_entry	*pe;
pe                919 drivers/nvme/target/fc.c 			struct nvmet_fc_port_entry *pe,
pe                924 drivers/nvme/target/fc.c 	pe->tgtport = tgtport;
pe                925 drivers/nvme/target/fc.c 	tgtport->pe = pe;
pe                927 drivers/nvme/target/fc.c 	pe->port = port;
pe                928 drivers/nvme/target/fc.c 	port->priv = pe;
pe                930 drivers/nvme/target/fc.c 	pe->node_name = tgtport->fc_target_port.node_name;
pe                931 drivers/nvme/target/fc.c 	pe->port_name = tgtport->fc_target_port.port_name;
pe                932 drivers/nvme/target/fc.c 	INIT_LIST_HEAD(&pe->pe_list);
pe                934 drivers/nvme/target/fc.c 	list_add_tail(&pe->pe_list, &nvmet_fc_portentry_list);
pe                938 drivers/nvme/target/fc.c nvmet_fc_portentry_unbind(struct nvmet_fc_port_entry *pe)
pe                943 drivers/nvme/target/fc.c 	if (pe->tgtport)
pe                944 drivers/nvme/target/fc.c 		pe->tgtport->pe = NULL;
pe                945 drivers/nvme/target/fc.c 	list_del(&pe->pe_list);
pe                957 drivers/nvme/target/fc.c 	struct nvmet_fc_port_entry *pe;
pe                961 drivers/nvme/target/fc.c 	pe = tgtport->pe;
pe                962 drivers/nvme/target/fc.c 	if (pe)
pe                963 drivers/nvme/target/fc.c 		pe->tgtport = NULL;
pe                964 drivers/nvme/target/fc.c 	tgtport->pe = NULL;
pe                979 drivers/nvme/target/fc.c 	struct nvmet_fc_port_entry *pe;
pe                983 drivers/nvme/target/fc.c 	list_for_each_entry(pe, &nvmet_fc_portentry_list, pe_list) {
pe                984 drivers/nvme/target/fc.c 		if (tgtport->fc_target_port.node_name == pe->node_name &&
pe                985 drivers/nvme/target/fc.c 		    tgtport->fc_target_port.port_name == pe->port_name) {
pe                986 drivers/nvme/target/fc.c 			WARN_ON(pe->tgtport);
pe                987 drivers/nvme/target/fc.c 			tgtport->pe = pe;
pe                988 drivers/nvme/target/fc.c 			pe->tgtport = tgtport;
pe               2158 drivers/nvme/target/fc.c 	if (!tgtport->pe)
pe               2188 drivers/nvme/target/fc.c 	fod->req.port = tgtport->pe->port;
pe               2499 drivers/nvme/target/fc.c 	struct nvmet_fc_port_entry *pe;
pe               2516 drivers/nvme/target/fc.c 	pe = kzalloc(sizeof(*pe), GFP_KERNEL);
pe               2517 drivers/nvme/target/fc.c 	if (!pe)
pe               2526 drivers/nvme/target/fc.c 			if (!tgtport->pe) {
pe               2527 drivers/nvme/target/fc.c 				nvmet_fc_portentry_bind(tgtport, pe, port);
pe               2537 drivers/nvme/target/fc.c 		kfree(pe);
pe               2545 drivers/nvme/target/fc.c 	struct nvmet_fc_port_entry *pe = port->priv;
pe               2547 drivers/nvme/target/fc.c 	nvmet_fc_portentry_unbind(pe);
pe               2549 drivers/nvme/target/fc.c 	kfree(pe);
pe               2555 drivers/nvme/target/fc.c 	struct nvmet_fc_port_entry *pe = port->priv;
pe               2556 drivers/nvme/target/fc.c 	struct nvmet_fc_tgtport *tgtport = pe->tgtport;
pe                443 drivers/parisc/eisa.c 		char *pe;
pe                445 drivers/parisc/eisa.c 		val = (int) simple_strtoul(cur, &pe, 0);
pe                757 drivers/pci/hotplug/pnv_php.c 	struct eeh_pe *pe;
pe                797 drivers/pci/hotplug/pnv_php.c 		pe = edev ? edev->pe : NULL;
pe                798 drivers/pci/hotplug/pnv_php.c 		if (pe) {
pe                800 drivers/pci/hotplug/pnv_php.c 			eeh_pe_mark_isolated(pe);
pe                802 drivers/pci/hotplug/pnv_php.c 			eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
pe               1658 drivers/pinctrl/tegra/pinctrl-tegra124.c 	FUNCTION(pe),
pe               1226 drivers/pinctrl/tegra/pinctrl-tegra210.c 	FUNCTION(pe),
pe                924 drivers/scsi/aic94xx/aic94xx_sds.c 		struct asd_ctrla_phy_entry *pe = &ps->phy_ent[i];
pe                928 drivers/scsi/aic94xx/aic94xx_sds.c 		if (*(u64 *)pe->sas_addr == 0) {
pe                933 drivers/scsi/aic94xx/aic94xx_sds.c 		memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr, pe->sas_addr,
pe                936 drivers/scsi/aic94xx/aic94xx_sds.c 			(pe->sas_link_rates & 0xF0) >> 4;
pe                938 drivers/scsi/aic94xx/aic94xx_sds.c 			(pe->sas_link_rates & 0x0F);
pe                940 drivers/scsi/aic94xx/aic94xx_sds.c 			(pe->sata_link_rates & 0xF0) >> 4;
pe                942 drivers/scsi/aic94xx/aic94xx_sds.c 			(pe->sata_link_rates & 0x0F);
pe                943 drivers/scsi/aic94xx/aic94xx_sds.c 		asd_ha->hw_prof.phy_desc[i].flags = pe->flags;
pe                163 drivers/scsi/cxlflash/ocxl_hw.c 	return ctx->pe;
pe                352 drivers/scsi/cxlflash/ocxl_hw.c 		ctx->psn_phys = afu->ppmmio_phys + (ctx->pe * ctx->psn_size);
pe                364 drivers/scsi/cxlflash/ocxl_hw.c 	rc = ocxl_link_add_pe(link_token, ctx->pe, pid, 0, 0, mm,
pe                415 drivers/scsi/cxlflash/ocxl_hw.c 					 ctx->pe);
pe                424 drivers/scsi/cxlflash/ocxl_hw.c 	rc = ocxl_link_remove_pe(afu->link_token, ctx->pe);
pe                509 drivers/scsi/cxlflash/ocxl_hw.c 	ctx->pe = rc;
pe                551 drivers/scsi/cxlflash/ocxl_hw.c 	idr_remove(&ctx->hw_afu->idr, ctx->pe);
pe                999 drivers/scsi/cxlflash/ocxl_hw.c 		__func__, ctx->pe, mask);
pe               1062 drivers/scsi/cxlflash/ocxl_hw.c 	event.header.process_element = ctx->pe;
pe               1233 drivers/scsi/cxlflash/ocxl_hw.c 	name = kasprintf(GFP_KERNEL, "ocxlflash:%d", ctx->pe);
pe               1279 drivers/scsi/cxlflash/ocxl_hw.c 		__func__, ctx->pe, irq);
pe               1324 drivers/scsi/cxlflash/ocxl_hw.c 				 dev_name(dev), ctx->pe, i);
pe                 55 drivers/scsi/cxlflash/ocxl_hw.h 	int pe;				/* Process element */
pe               2219 drivers/scsi/isci/host.c 					    &ihost->scu_registers->peg0.pe[i].tl,
pe               2220 drivers/scsi/isci/host.c 					    &ihost->scu_registers->peg0.pe[i].ll);
pe                440 drivers/scsi/isci/registers.h #define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \
pe                441 drivers/scsi/isci/registers.h 	((1 << (pe)) << ((peg) * 8))
pe               1819 drivers/scsi/isci/registers.h 	struct transport_link_layer_pair pe[4];
pe               3027 drivers/scsi/lpfc/lpfc_ct.c 	struct lpfc_fdmi_port_entry *pe;
pe               3092 drivers/scsi/lpfc/lpfc_ct.c 			memcpy(&rh->rpl.pe, &phba->pport->fc_sparam.portName,
pe               3184 drivers/scsi/lpfc/lpfc_ct.c 		pe = (struct lpfc_fdmi_port_entry *)&CtReq->un.PortID;
pe               3185 drivers/scsi/lpfc/lpfc_ct.c 		memcpy((uint8_t *)&pe->PortName,
pe               3197 drivers/scsi/lpfc/lpfc_ct.c 		pe = (struct lpfc_fdmi_port_entry *)&CtReq->un.PortID;
pe               3198 drivers/scsi/lpfc/lpfc_ct.c 		memcpy((uint8_t *)&pe->PortName,
pe               1348 drivers/scsi/lpfc/lpfc_hw.h 	uint32_t pe;		/* Variable-length array */
pe                661 drivers/scsi/ncr53c8xx.c 		char *pe;
pe                672 drivers/scsi/ncr53c8xx.c 			val = (int) simple_strtoul(pv, &pe, 0);
pe                677 drivers/scsi/ncr53c8xx.c 			if (pe && *pe == '/') {
pe                679 drivers/scsi/ncr53c8xx.c 				while (*pe && *pe != ARG_SEP && 
pe                681 drivers/scsi/ncr53c8xx.c 					driver_setup.tag_ctrl[i++] = *pe++;
pe                413 drivers/thunderbolt/property.c 		struct tb_property_dir_entry *pe;
pe                415 drivers/thunderbolt/property.c 		pe = (struct tb_property_dir_entry *)&block[start_offset];
pe                416 drivers/thunderbolt/property.c 		memcpy(pe->uuid, dir->uuid, sizeof(pe->uuid));
pe                417 drivers/thunderbolt/property.c 		entry = pe->entries;
pe                194 drivers/tty/vt/selection.c 	int i, ps, pe, multiplier;
pe                205 drivers/tty/vt/selection.c 	pe = v->ye * vc->vc_size_row + (v->xe << 1);
pe                219 drivers/tty/vt/selection.c 	if (ps > pe)	/* make sel_start <= sel_end */
pe                220 drivers/tty/vt/selection.c 		swap(ps, pe);
pe                236 drivers/tty/vt/selection.c 			new_sel_end = pe;
pe                249 drivers/tty/vt/selection.c 			spc = isspace(sel_pos(pe));
pe                250 drivers/tty/vt/selection.c 			for (new_sel_end = pe; ; pe += 2)
pe                252 drivers/tty/vt/selection.c 				if ((spc && !isspace(sel_pos(pe))) ||
pe                253 drivers/tty/vt/selection.c 				    (!spc && !inword(sel_pos(pe))))
pe                255 drivers/tty/vt/selection.c 				new_sel_end = pe;
pe                256 drivers/tty/vt/selection.c 				if (!((pe + 2) % vc->vc_size_row))
pe                262 drivers/tty/vt/selection.c 			new_sel_end = pe + vc->vc_size_row
pe                263 drivers/tty/vt/selection.c 				    - pe % vc->vc_size_row - 2;
pe                266 drivers/tty/vt/selection.c 			highlight_pointer(pe);
pe                279 drivers/tty/vt/selection.c 		for (pe = new_sel_end + 2; ; pe += 2)
pe                280 drivers/tty/vt/selection.c 			if (!isspace(sel_pos(pe)) ||
pe                281 drivers/tty/vt/selection.c 			    atedge(pe, vc->vc_size_row))
pe                283 drivers/tty/vt/selection.c 		if (isspace(sel_pos(pe)))
pe                284 drivers/tty/vt/selection.c 			new_sel_end = pe;
pe                 34 drivers/vfio/vfio_spapr_eeh.c 	struct eeh_pe *pe;
pe                 47 drivers/vfio/vfio_spapr_eeh.c 		pe = eeh_iommu_group_to_pe(group);
pe                 48 drivers/vfio/vfio_spapr_eeh.c 		if (!pe)
pe                 59 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_set_option(pe, EEH_OPT_DISABLE);
pe                 62 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_set_option(pe, EEH_OPT_ENABLE);
pe                 65 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_set_option(pe, EEH_OPT_THAW_MMIO);
pe                 68 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_set_option(pe, EEH_OPT_THAW_DMA);
pe                 71 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_get_state(pe);
pe                 74 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE, true);
pe                 77 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_reset(pe, EEH_RESET_HOT, true);
pe                 80 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_reset(pe, EEH_RESET_FUNDAMENTAL, true);
pe                 83 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_configure(pe);
pe                 92 drivers/vfio/vfio_spapr_eeh.c 			ret = eeh_pe_inject_err(pe, op.err.type, op.err.func,
pe                280 fs/f2fs/acl.c  	struct posix_acl_entry *pa, *pe;
pe                287 fs/f2fs/acl.c  	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                221 fs/nfs_common/nfsacl.c 	struct posix_acl_entry *pa, *pe,
pe                231 fs/nfs_common/nfsacl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                191 fs/nfsd/nfs4acl.c 	struct posix_acl_entry *pa, *pe;
pe                201 fs/nfsd/nfs4acl.c 	pe = acl->a_entries + acl->a_count;
pe                203 fs/nfsd/nfs4acl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                212 fs/posix_acl.c 	const struct posix_acl_entry *pa, *pe;
pe                216 fs/posix_acl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                281 fs/posix_acl.c 	const struct posix_acl_entry *pa, *pe;
pe                291 fs/posix_acl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                350 fs/posix_acl.c 	const struct posix_acl_entry *pa, *pe, *mask_obj;
pe                355 fs/posix_acl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                394 fs/posix_acl.c 	for (mask_obj = pa+1; mask_obj != pe; mask_obj++) {
pe                418 fs/posix_acl.c 	struct posix_acl_entry *pa, *pe;
pe                425 fs/posix_acl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                476 fs/posix_acl.c 	struct posix_acl_entry *pa, *pe;
pe                480 fs/posix_acl.c 	FOREACH_ACL_ENTRY(pa, acl, pe) {
pe                 34 include/linux/posix_acl.h #define FOREACH_ACL_ENTRY(pa, acl, pe) \
pe                 35 include/linux/posix_acl.h 	for(pa=(acl)->a_entries, pe=pa+(acl)->a_count; pa<pe; pa++)
pe                498 include/net/ip_vs.h 	const struct ip_vs_pe		*pe;
pe                557 include/net/ip_vs.h 	const struct ip_vs_pe	*pe;
pe                639 include/net/ip_vs.h 	struct ip_vs_pe __rcu	*pe;
pe               1195 include/net/ip_vs.h 	p->pe = NULL;
pe               1348 include/net/ip_vs.h int register_ip_vs_pe(struct ip_vs_pe *pe);
pe               1349 include/net/ip_vs.h int unregister_ip_vs_pe(struct ip_vs_pe *pe);
pe               1354 include/net/ip_vs.h #define ip_vs_pe_get(pe)			\
pe               1355 include/net/ip_vs.h 	if (pe && pe->module)			\
pe               1356 include/net/ip_vs.h 		__module_get(pe->module);
pe               1358 include/net/ip_vs.h #define ip_vs_pe_put(pe)			\
pe               1359 include/net/ip_vs.h 	if (pe && pe->module)			\
pe               1360 include/net/ip_vs.h 		module_put(pe->module);
pe                371 kernel/time/timer_list.c 	struct proc_dir_entry *pe;
pe                373 kernel/time/timer_list.c 	pe = proc_create_seq_private("timer_list", 0400, NULL, &timer_list_sops,
pe                375 kernel/time/timer_list.c 	if (!pe)
pe                133 kernel/trace/trace_events_filter.c static void parse_error(struct filter_parse_error *pe, int err, int pos)
pe                135 kernel/trace/trace_events_filter.c 	pe->lasterr = err;
pe                136 kernel/trace/trace_events_filter.c 	pe->lasterr_pos = pos;
pe                140 kernel/trace/trace_events_filter.c 			     struct filter_parse_error *pe,
pe                412 kernel/trace/trace_events_filter.c 		struct filter_parse_error *pe)
pe                433 kernel/trace/trace_events_filter.c 		parse_error(pe, -ENOMEM, 0);
pe                438 kernel/trace/trace_events_filter.c 		parse_error(pe, -ENOMEM, 0);
pe                469 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_TOO_MANY_PREDS, next - str);
pe                476 kernel/trace/trace_events_filter.c 		len = parse_pred(next, data, ptr - str, pe, &prog[N].pred);
pe                504 kernel/trace/trace_events_filter.c 				parse_error(pe, FILT_ERR_TOO_MANY_PREDS,
pe                533 kernel/trace/trace_events_filter.c 				parse_error(pe, FILT_ERR_TOO_MANY_CLOSE, ptr - str);
pe                542 kernel/trace/trace_events_filter.c 		parse_error(pe, FILT_ERR_TOO_MANY_OPEN, ptr - str);
pe                549 kernel/trace/trace_events_filter.c 		parse_error(pe, FILT_ERR_NO_FILTER, ptr - str);
pe                930 kernel/trace/trace_events_filter.c 			      struct filter_parse_error *pe,
pe                934 kernel/trace/trace_events_filter.c 	int pos = pe->lasterr_pos;
pe                955 kernel/trace/trace_events_filter.c 	if (pe->lasterr > 0) {
pe                957 kernel/trace/trace_events_filter.c 		trace_seq_printf(s, "\nparse_error: %s\n", err_text[pe->lasterr]);
pe                960 kernel/trace/trace_events_filter.c 				pe->lasterr, pe->lasterr_pos);
pe                962 kernel/trace/trace_events_filter.c 		trace_seq_printf(s, "\nError: (%d)\n", pe->lasterr);
pe               1153 kernel/trace/trace_events_filter.c 		      int pos, struct filter_parse_error *pe,
pe               1191 kernel/trace/trace_events_filter.c 		parse_error(pe, FILT_ERR_FIELD_NOT_FOUND, pos + i);
pe               1206 kernel/trace/trace_events_filter.c 		parse_error(pe, FILT_ERR_INVALID_OP, pos + i);
pe               1234 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_IP_FIELD_ONLY, pos + i);
pe               1260 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);
pe               1281 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);
pe               1287 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_EXPECT_DIGIT, pos + i);
pe               1296 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_MISSING_QUOTE, pos + i);
pe               1304 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);
pe               1332 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_EXPECT_STRING, pos + i);
pe               1337 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);
pe               1351 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);
pe               1364 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_ILLEGAL_INTVAL, pos + s);
pe               1380 kernel/trace/trace_events_filter.c 		parse_error(pe, FILT_ERR_INVALID_VALUE, pos + i);
pe               1508 kernel/trace/trace_events_filter.c 			 struct filter_parse_error *pe)
pe               1520 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_MISSING_QUOTE, index);
pe               1523 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_TOO_MANY_OPEN, index);
pe               1526 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_TOO_MANY_CLOSE, index);
pe               1535 kernel/trace/trace_events_filter.c 			       parse_pred, call, pe);
pe               1592 kernel/trace/trace_events_filter.c 				struct filter_parse_error *pe,
pe               1616 kernel/trace/trace_events_filter.c 		err = process_preds(file->event_call, filter_string, filter, pe);
pe               1619 kernel/trace/trace_events_filter.c 			parse_error(pe, FILT_ERR_BAD_SUBSYS_FILTER, 0);
pe               1620 kernel/trace/trace_events_filter.c 			append_filter_err(tr, pe, filter);
pe               1662 kernel/trace/trace_events_filter.c 	parse_error(pe, FILT_ERR_BAD_SUBSYS_FILTER, 0);
pe               1682 kernel/trace/trace_events_filter.c 	struct filter_parse_error *pe = NULL;
pe               1695 kernel/trace/trace_events_filter.c 	pe = kzalloc(sizeof(*pe), GFP_KERNEL);
pe               1697 kernel/trace/trace_events_filter.c 	if (!filter || !pe || err) {
pe               1698 kernel/trace/trace_events_filter.c 		kfree(pe);
pe               1705 kernel/trace/trace_events_filter.c 	*pse = pe;
pe               1710 kernel/trace/trace_events_filter.c static void create_filter_finish(struct filter_parse_error *pe)
pe               1712 kernel/trace/trace_events_filter.c 	kfree(pe);
pe               1737 kernel/trace/trace_events_filter.c 	struct filter_parse_error *pe = NULL;
pe               1744 kernel/trace/trace_events_filter.c 	err = create_filter_start(filter_string, set_str, &pe, filterp);
pe               1748 kernel/trace/trace_events_filter.c 	err = process_preds(call, filter_string, *filterp, pe);
pe               1750 kernel/trace/trace_events_filter.c 		append_filter_err(tr, pe, *filterp);
pe               1751 kernel/trace/trace_events_filter.c 	create_filter_finish(pe);
pe               1777 kernel/trace/trace_events_filter.c 	struct filter_parse_error *pe = NULL;
pe               1780 kernel/trace/trace_events_filter.c 	err = create_filter_start(filter_str, true, &pe, filterp);
pe               1782 kernel/trace/trace_events_filter.c 		err = process_system_preds(dir, tr, pe, filter_str);
pe               1788 kernel/trace/trace_events_filter.c 			append_filter_err(tr, pe, *filterp);
pe               1791 kernel/trace/trace_events_filter.c 	create_filter_finish(pe);
pe                623 lib/crypto/des.c static unsigned long des_ekey(u32 *pe, const u8 *k)
pe                634 lib/crypto/des.c 	pe[15 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d];
pe                635 lib/crypto/des.c 	pe[14 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                636 lib/crypto/des.c 	pe[13 * 2 + 0] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                637 lib/crypto/des.c 	pe[12 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                638 lib/crypto/des.c 	pe[11 * 2 + 0] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                639 lib/crypto/des.c 	pe[10 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                640 lib/crypto/des.c 	pe[ 9 * 2 + 0] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                641 lib/crypto/des.c 	pe[ 8 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c];
pe                642 lib/crypto/des.c 	pe[ 7 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                643 lib/crypto/des.c 	pe[ 6 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                644 lib/crypto/des.c 	pe[ 5 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                645 lib/crypto/des.c 	pe[ 4 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                646 lib/crypto/des.c 	pe[ 3 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                647 lib/crypto/des.c 	pe[ 2 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                648 lib/crypto/des.c 	pe[ 1 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b];
pe                649 lib/crypto/des.c 	pe[ 0 * 2 + 0] = DES_PC2(b, c, d, a);
pe                665 lib/crypto/des.c 	pe[15 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d];
pe                666 lib/crypto/des.c 	pe[14 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                667 lib/crypto/des.c 	pe[13 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                668 lib/crypto/des.c 	pe[12 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                669 lib/crypto/des.c 	pe[11 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                670 lib/crypto/des.c 	pe[10 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                671 lib/crypto/des.c 	pe[ 9 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                672 lib/crypto/des.c 	pe[ 8 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c];
pe                673 lib/crypto/des.c 	pe[ 7 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                674 lib/crypto/des.c 	pe[ 6 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                675 lib/crypto/des.c 	pe[ 5 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                676 lib/crypto/des.c 	pe[ 4 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                677 lib/crypto/des.c 	pe[ 3 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                678 lib/crypto/des.c 	pe[ 2 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                679 lib/crypto/des.c 	pe[ 1 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b];
pe                680 lib/crypto/des.c 	pe[ 0 * 2 + 1] = DES_PC2(b, c, d, a);
pe                684 lib/crypto/des.c 		a = pe[2 * d];
pe                685 lib/crypto/des.c 		b = pe[2 * d + 1];
pe                691 lib/crypto/des.c 		pe[2 * d] = a;
pe                692 lib/crypto/des.c 		pe[2 * d + 1] = b;
pe                714 lib/crypto/des.c static void dkey(u32 *pe, const u8 *k)
pe                725 lib/crypto/des.c 	pe[ 0 * 2] = DES_PC2(a, b, c, d); d = rs[d];
pe                726 lib/crypto/des.c 	pe[ 1 * 2] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                727 lib/crypto/des.c 	pe[ 2 * 2] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                728 lib/crypto/des.c 	pe[ 3 * 2] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                729 lib/crypto/des.c 	pe[ 4 * 2] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                730 lib/crypto/des.c 	pe[ 5 * 2] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                731 lib/crypto/des.c 	pe[ 6 * 2] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                732 lib/crypto/des.c 	pe[ 7 * 2] = DES_PC2(d, a, b, c); c = rs[c];
pe                733 lib/crypto/des.c 	pe[ 8 * 2] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                734 lib/crypto/des.c 	pe[ 9 * 2] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                735 lib/crypto/des.c 	pe[10 * 2] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                736 lib/crypto/des.c 	pe[11 * 2] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                737 lib/crypto/des.c 	pe[12 * 2] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                738 lib/crypto/des.c 	pe[13 * 2] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                739 lib/crypto/des.c 	pe[14 * 2] = DES_PC2(c, d, a, b); b = rs[b];
pe                740 lib/crypto/des.c 	pe[15 * 2] = DES_PC2(b, c, d, a);
pe                750 lib/crypto/des.c 	pe[ 0 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d];
pe                751 lib/crypto/des.c 	pe[ 1 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                752 lib/crypto/des.c 	pe[ 2 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                753 lib/crypto/des.c 	pe[ 3 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                754 lib/crypto/des.c 	pe[ 4 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                755 lib/crypto/des.c 	pe[ 5 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];
pe                756 lib/crypto/des.c 	pe[ 6 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];
pe                757 lib/crypto/des.c 	pe[ 7 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c];
pe                758 lib/crypto/des.c 	pe[ 8 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                759 lib/crypto/des.c 	pe[ 9 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                760 lib/crypto/des.c 	pe[10 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                761 lib/crypto/des.c 	pe[11 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                762 lib/crypto/des.c 	pe[12 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];
pe                763 lib/crypto/des.c 	pe[13 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];
pe                764 lib/crypto/des.c 	pe[14 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b];
pe                765 lib/crypto/des.c 	pe[15 * 2 + 1] = DES_PC2(b, c, d, a);
pe                769 lib/crypto/des.c 		a = pe[2 * d];
pe                770 lib/crypto/des.c 		b = pe[2 * d + 1];
pe                776 lib/crypto/des.c 		pe[2 * d] = a;
pe                777 lib/crypto/des.c 		pe[2 * d + 1] = b;
pe                826 lib/crypto/des.c 	u32 *pe = ctx->expkey;
pe                836 lib/crypto/des.c 	des_ekey(pe, key); pe += DES_EXPKEY_WORDS; key += DES_KEY_SIZE;
pe                837 lib/crypto/des.c 	dkey(pe, key); pe += DES_EXPKEY_WORDS; key += DES_KEY_SIZE;
pe                838 lib/crypto/des.c 	des_ekey(pe, key);
pe               3680 net/core/pktgen.c 	struct proc_dir_entry *pe;
pe               3711 net/core/pktgen.c 	pe = proc_create_data(t->tsk->comm, 0600, pn->proc_dir,
pe               3713 net/core/pktgen.c 	if (!pe) {
pe               3786 net/core/pktgen.c 	struct proc_dir_entry *pe;
pe               3797 net/core/pktgen.c 	pe = proc_create(PGCTRL, 0600, pn->proc_dir, &pktgen_fops);
pe               3798 net/core/pktgen.c 	if (pe == NULL) {
pe                128 net/netfilter/ipvs/ip_vs_conn.c 	if (p->pe_data && p->pe->hashkey_raw)
pe                129 net/netfilter/ipvs/ip_vs_conn.c 		return p->pe->hashkey_raw(p, ip_vs_conn_rnd, inverse) &
pe                150 net/netfilter/ipvs/ip_vs_conn.c 	if (cp->pe) {
pe                151 net/netfilter/ipvs/ip_vs_conn.c 		p.pe = cp->pe;
pe                359 net/netfilter/ipvs/ip_vs_conn.c 		if (unlikely(p->pe_data && p->pe->ct_match)) {
pe                362 net/netfilter/ipvs/ip_vs_conn.c 			if (p->pe == cp->pe && p->pe->ct_match(p, cp)) {
pe                805 net/netfilter/ipvs/ip_vs_conn.c 	ip_vs_pe_put(cp->pe);
pe                932 net/netfilter/ipvs/ip_vs_conn.c 	if (flags & IP_VS_CONN_F_TEMPLATE && p->pe) {
pe                933 net/netfilter/ipvs/ip_vs_conn.c 		ip_vs_pe_get(p->pe);
pe                934 net/netfilter/ipvs/ip_vs_conn.c 		cp->pe = p->pe;
pe                938 net/netfilter/ipvs/ip_vs_conn.c 		cp->pe = NULL;
pe               1096 net/netfilter/ipvs/ip_vs_conn.c 			len = strlen(cp->pe->name);
pe               1097 net/netfilter/ipvs/ip_vs_conn.c 			memcpy(pe_data + 1, cp->pe->name, len);
pe               1100 net/netfilter/ipvs/ip_vs_conn.c 			len += cp->pe->show_pe_data(cp, pe_data + len);
pe                250 net/netfilter/ipvs/ip_vs_core.c 	p->pe = rcu_dereference(svc->pe);
pe                251 net/netfilter/ipvs/ip_vs_core.c 	if (p->pe && p->pe->fill_param)
pe                252 net/netfilter/ipvs/ip_vs_core.c 		return p->pe->fill_param(p, skb);
pe               1262 net/netfilter/ipvs/ip_vs_core.c 		struct ip_vs_pe *pe;
pe               1266 net/netfilter/ipvs/ip_vs_core.c 			pe = rcu_dereference(svc->pe);
pe               1267 net/netfilter/ipvs/ip_vs_core.c 			if (pe && pe->conn_out)
pe               1268 net/netfilter/ipvs/ip_vs_core.c 				cp = pe->conn_out(svc, dest, skb, iph,
pe               1273 net/netfilter/ipvs/ip_vs_ctl.c 	struct ip_vs_pe *pe = NULL;
pe               1292 net/netfilter/ipvs/ip_vs_ctl.c 		pe = ip_vs_pe_getbyname(u->pe_name);
pe               1293 net/netfilter/ipvs/ip_vs_ctl.c 		if (pe == NULL) {
pe               1361 net/netfilter/ipvs/ip_vs_ctl.c 	RCU_INIT_POINTER(svc->pe, pe);
pe               1362 net/netfilter/ipvs/ip_vs_ctl.c 	pe = NULL;
pe               1369 net/netfilter/ipvs/ip_vs_ctl.c 	if (svc->pe && svc->pe->conn_out)
pe               1393 net/netfilter/ipvs/ip_vs_ctl.c 	ip_vs_pe_put(pe);
pe               1409 net/netfilter/ipvs/ip_vs_ctl.c 	struct ip_vs_pe *pe = NULL, *old_pe = NULL;
pe               1427 net/netfilter/ipvs/ip_vs_ctl.c 		pe = ip_vs_pe_getbyname(u->pe_name);
pe               1428 net/netfilter/ipvs/ip_vs_ctl.c 		if (pe == NULL) {
pe               1434 net/netfilter/ipvs/ip_vs_ctl.c 		old_pe = pe;
pe               1473 net/netfilter/ipvs/ip_vs_ctl.c 	old_pe = rcu_dereference_protected(svc->pe, 1);
pe               1474 net/netfilter/ipvs/ip_vs_ctl.c 	if (pe != old_pe) {
pe               1475 net/netfilter/ipvs/ip_vs_ctl.c 		rcu_assign_pointer(svc->pe, pe);
pe               1477 net/netfilter/ipvs/ip_vs_ctl.c 		new_pe_conn_out = (pe && pe->conn_out) ? true : false;
pe               1515 net/netfilter/ipvs/ip_vs_ctl.c 	old_pe = rcu_dereference_protected(svc->pe, 1);
pe               3033 net/netfilter/ipvs/ip_vs_ctl.c 	struct ip_vs_pe *pe;
pe               3058 net/netfilter/ipvs/ip_vs_ctl.c 	pe = rcu_dereference_protected(svc->pe, 1);
pe               3060 net/netfilter/ipvs/ip_vs_ctl.c 	    (pe && nla_put_string(skb, IPVS_SVC_ATTR_PE_NAME, pe->name)) ||
pe                 23 net/netfilter/ipvs/ip_vs_pe.c 	struct ip_vs_pe *pe;
pe                 29 net/netfilter/ipvs/ip_vs_pe.c 	list_for_each_entry_rcu(pe, &ip_vs_pe, n_list) {
pe                 31 net/netfilter/ipvs/ip_vs_pe.c 		if (pe->module &&
pe                 32 net/netfilter/ipvs/ip_vs_pe.c 		    !try_module_get(pe->module)) {
pe                 36 net/netfilter/ipvs/ip_vs_pe.c 		if (strcmp(pe_name, pe->name)==0) {
pe                 39 net/netfilter/ipvs/ip_vs_pe.c 			return pe;
pe                 41 net/netfilter/ipvs/ip_vs_pe.c 		module_put(pe->module);
pe                 51 net/netfilter/ipvs/ip_vs_pe.c 	struct ip_vs_pe *pe;
pe                 54 net/netfilter/ipvs/ip_vs_pe.c 	pe = __ip_vs_pe_getbyname(name);
pe                 57 net/netfilter/ipvs/ip_vs_pe.c 	if (!pe) {
pe                 59 net/netfilter/ipvs/ip_vs_pe.c 		pe = __ip_vs_pe_getbyname(name);
pe                 62 net/netfilter/ipvs/ip_vs_pe.c 	return pe;
pe                 66 net/netfilter/ipvs/ip_vs_pe.c int register_ip_vs_pe(struct ip_vs_pe *pe)
pe                 79 net/netfilter/ipvs/ip_vs_pe.c 		if (strcmp(tmp->name, pe->name) == 0) {
pe                 83 net/netfilter/ipvs/ip_vs_pe.c 			       "in the system\n", __func__, pe->name);
pe                 88 net/netfilter/ipvs/ip_vs_pe.c 	list_add_rcu(&pe->n_list, &ip_vs_pe);
pe                 91 net/netfilter/ipvs/ip_vs_pe.c 	pr_info("[%s] pe registered.\n", pe->name);
pe                 98 net/netfilter/ipvs/ip_vs_pe.c int unregister_ip_vs_pe(struct ip_vs_pe *pe)
pe                102 net/netfilter/ipvs/ip_vs_pe.c 	list_del_rcu(&pe->n_list);
pe                108 net/netfilter/ipvs/ip_vs_pe.c 	pr_info("[%s] pe unregistered.\n", pe->name);
pe                662 net/netfilter/ipvs/ip_vs_sync.c 		pe_name_len = strnlen(cp->pe->name, IP_VS_PENAME_MAXLEN);
pe                769 net/netfilter/ipvs/ip_vs_sync.c 			memcpy(p, cp->pe->name, pe_name_len);
pe                818 net/netfilter/ipvs/ip_vs_sync.c 			p->pe = __ip_vs_pe_getbyname(buff);
pe                819 net/netfilter/ipvs/ip_vs_sync.c 			if (!p->pe) {
pe                831 net/netfilter/ipvs/ip_vs_sync.c 			module_put(p->pe->module);
pe               1194 net/netfilter/ipvs/ip_vs_sync.c 	ip_vs_pe_put(param.pe);
pe                 35 scripts/genksyms/parse.y remove_list(struct string_list **pb, struct string_list **pe)
pe                 37 scripts/genksyms/parse.y   struct string_list *b = *pb, *e = *pe;
pe                 44 tools/perf/arch/x86/tests/intel-cqm.c 	struct perf_event_attr pe;
pe                 72 tools/perf/arch/x86/tests/intel-cqm.c 	memset(&pe, 0, sizeof(pe));
pe                 73 tools/perf/arch/x86/tests/intel-cqm.c 	pe.size = sizeof(pe);
pe                 75 tools/perf/arch/x86/tests/intel-cqm.c 	pe.type = PERF_TYPE_HARDWARE;
pe                 76 tools/perf/arch/x86/tests/intel-cqm.c 	pe.config = PERF_COUNT_HW_CPU_CYCLES;
pe                 77 tools/perf/arch/x86/tests/intel-cqm.c 	pe.read_format = PERF_FORMAT_GROUP;
pe                 79 tools/perf/arch/x86/tests/intel-cqm.c 	pe.sample_period = 128;
pe                 80 tools/perf/arch/x86/tests/intel-cqm.c 	pe.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_READ;
pe                 84 tools/perf/arch/x86/tests/intel-cqm.c 	fd[0] = sys_perf_event_open(&pe, pid, -1, -1, flag);
pe                 90 tools/perf/arch/x86/tests/intel-cqm.c 	memset(&pe, 0, sizeof(pe));
pe                 91 tools/perf/arch/x86/tests/intel-cqm.c 	pe.size = sizeof(pe);
pe                 93 tools/perf/arch/x86/tests/intel-cqm.c 	pe.type = evsel->attr.type;
pe                 94 tools/perf/arch/x86/tests/intel-cqm.c 	pe.config = evsel->attr.config;
pe                 96 tools/perf/arch/x86/tests/intel-cqm.c 	fd[1] = sys_perf_event_open(&pe, pid, -1, fd[0], flag);
pe                101 tools/perf/tests/bp_signal.c 	struct perf_event_attr pe;
pe                104 tools/perf/tests/bp_signal.c 	memset(&pe, 0, sizeof(struct perf_event_attr));
pe                105 tools/perf/tests/bp_signal.c 	pe.type = PERF_TYPE_BREAKPOINT;
pe                106 tools/perf/tests/bp_signal.c 	pe.size = sizeof(struct perf_event_attr);
pe                108 tools/perf/tests/bp_signal.c 	pe.config = 0;
pe                109 tools/perf/tests/bp_signal.c 	pe.bp_type = is_x ? HW_BREAKPOINT_X : HW_BREAKPOINT_W;
pe                110 tools/perf/tests/bp_signal.c 	pe.bp_addr = (unsigned long) addr;
pe                111 tools/perf/tests/bp_signal.c 	pe.bp_len = sizeof(long);
pe                113 tools/perf/tests/bp_signal.c 	pe.sample_period = 1;
pe                114 tools/perf/tests/bp_signal.c 	pe.sample_type = PERF_SAMPLE_IP;
pe                115 tools/perf/tests/bp_signal.c 	pe.wakeup_events = 1;
pe                117 tools/perf/tests/bp_signal.c 	pe.disabled = 1;
pe                118 tools/perf/tests/bp_signal.c 	pe.exclude_kernel = 1;
pe                119 tools/perf/tests/bp_signal.c 	pe.exclude_hv = 1;
pe                121 tools/perf/tests/bp_signal.c 	fd = sys_perf_event_open(&pe, 0, -1, -1,
pe                124 tools/perf/tests/bp_signal.c 		pr_debug("failed opening event %llx\n", pe.config);
pe                 64 tools/perf/tests/bp_signal_overflow.c 	struct perf_event_attr pe;
pe                 79 tools/perf/tests/bp_signal_overflow.c 	memset(&pe, 0, sizeof(struct perf_event_attr));
pe                 80 tools/perf/tests/bp_signal_overflow.c 	pe.type = PERF_TYPE_BREAKPOINT;
pe                 81 tools/perf/tests/bp_signal_overflow.c 	pe.size = sizeof(struct perf_event_attr);
pe                 83 tools/perf/tests/bp_signal_overflow.c 	pe.config = 0;
pe                 84 tools/perf/tests/bp_signal_overflow.c 	pe.bp_type = HW_BREAKPOINT_X;
pe                 85 tools/perf/tests/bp_signal_overflow.c 	pe.bp_addr = (unsigned long) test_function;
pe                 86 tools/perf/tests/bp_signal_overflow.c 	pe.bp_len = sizeof(long);
pe                 88 tools/perf/tests/bp_signal_overflow.c 	pe.sample_period = THRESHOLD;
pe                 89 tools/perf/tests/bp_signal_overflow.c 	pe.sample_type = PERF_SAMPLE_IP;
pe                 90 tools/perf/tests/bp_signal_overflow.c 	pe.wakeup_events = 1;
pe                 92 tools/perf/tests/bp_signal_overflow.c 	pe.disabled = 1;
pe                 93 tools/perf/tests/bp_signal_overflow.c 	pe.exclude_kernel = 1;
pe                 94 tools/perf/tests/bp_signal_overflow.c 	pe.exclude_hv = 1;
pe                 96 tools/perf/tests/bp_signal_overflow.c 	fd = sys_perf_event_open(&pe, 0, -1, -1,
pe                 99 tools/perf/tests/bp_signal_overflow.c 		pr_debug("failed opening event %llx\n", pe.config);
pe                303 tools/perf/util/metricgroup.c 	struct pmu_event *pe;
pe                324 tools/perf/util/metricgroup.c 		pe = &map->table[i];
pe                326 tools/perf/util/metricgroup.c 		if (!pe->name && !pe->metric_group && !pe->metric_name)
pe                328 tools/perf/util/metricgroup.c 		if (!pe->metric_expr)
pe                330 tools/perf/util/metricgroup.c 		g = pe->metric_group;
pe                331 tools/perf/util/metricgroup.c 		if (!g && pe->metric_name) {
pe                332 tools/perf/util/metricgroup.c 			if (pe->name)
pe                353 tools/perf/util/metricgroup.c 					s = (char *)pe->metric_name;
pe                356 tools/perf/util/metricgroup.c 						     pe->metric_name, 8, "[", pe->desc) < 0)
pe                361 tools/perf/util/metricgroup.c 							     s, 8, "[", pe->metric_expr) < 0)
pe                406 tools/perf/util/metricgroup.c 	struct pmu_event *pe;
pe                414 tools/perf/util/metricgroup.c 		pe = &map->table[i];
pe                416 tools/perf/util/metricgroup.c 		if (!pe->name && !pe->metric_group && !pe->metric_name)
pe                418 tools/perf/util/metricgroup.c 		if (!pe->metric_expr)
pe                420 tools/perf/util/metricgroup.c 		if (match_metric(pe->metric_group, metric) ||
pe                421 tools/perf/util/metricgroup.c 		    match_metric(pe->metric_name, metric)) {
pe                427 tools/perf/util/metricgroup.c 			pr_debug("metric expr %s for %s\n", pe->metric_expr, pe->metric_name);
pe                429 tools/perf/util/metricgroup.c 			if (expr__find_other(pe->metric_expr,
pe                463 tools/perf/util/metricgroup.c 			eg->metric_name = pe->metric_name;
pe                464 tools/perf/util/metricgroup.c 			eg->metric_expr = pe->metric_expr;
pe                465 tools/perf/util/metricgroup.c 			eg->metric_unit = pe->unit;
pe                546 tools/perf/util/metricgroup.c 	struct pmu_event *pe;
pe                553 tools/perf/util/metricgroup.c 		pe = &map->table[i];
pe                555 tools/perf/util/metricgroup.c 		if (!pe->name && !pe->metric_group && !pe->metric_name)
pe                557 tools/perf/util/metricgroup.c 		if (!pe->metric_expr)
pe                559 tools/perf/util/metricgroup.c 		if (match_metric(pe->metric_name, metric))
pe                767 tools/perf/util/pmu.c 		struct pmu_event *pe = &map->table[i++];
pe                768 tools/perf/util/pmu.c 		const char *pname = pe->pmu ? pe->pmu : cpu_name;
pe                770 tools/perf/util/pmu.c 		if (!pe->name) {
pe                771 tools/perf/util/pmu.c 			if (pe->metric_group || pe->metric_name)
pe                785 tools/perf/util/pmu.c 		__perf_pmu__new_alias(head, NULL, (char *)pe->name,
pe                786 tools/perf/util/pmu.c 				(char *)pe->desc, (char *)pe->event,
pe                787 tools/perf/util/pmu.c 				(char *)pe->long_desc, (char *)pe->topic,
pe                788 tools/perf/util/pmu.c 				(char *)pe->unit, (char *)pe->perpkg,
pe                789 tools/perf/util/pmu.c 				(char *)pe->metric_expr,
pe                790 tools/perf/util/pmu.c 				(char *)pe->metric_name);
pe                355 tools/perf/util/python.c tracepoint_field(struct pyrf_event *pe, struct tep_format_field *field)
pe                358 tools/perf/util/python.c 	void *data = pe->sample.raw_data;
pe               1573 tools/testing/selftests/net/nettest.c 	struct protoent *pe;
pe               1625 tools/testing/selftests/net/nettest.c 			pe = getprotobyname(optarg);
pe               1626 tools/testing/selftests/net/nettest.c 			if (pe) {
pe               1627 tools/testing/selftests/net/nettest.c 				args.protocol = pe->p_proto;