pdc_write         467 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
pdc_write         468 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
pdc_write         469 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
pdc_write         470 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
pdc_write         471 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
pdc_write         474 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
pdc_write         475 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write         476 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
pdc_write         477 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
pdc_write         478 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
pdc_write         479 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
pdc_write         480 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
pdc_write         481 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
pdc_write         482 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
pdc_write         483 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
pdc_write         484 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
pdc_write         485 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
pdc_write         486 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
pdc_write         487 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write         488 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
pdc_write         489 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
pdc_write         490 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
pdc_write         491 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
pdc_write         492 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
pdc_write         493 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
pdc_write         494 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
pdc_write         495 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
pdc_write         496 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
pdc_write         497 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
pdc_write         500 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
pdc_write         501 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
pdc_write         137 drivers/irqchip/irq-imgpdc.c 	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
pdc_write         147 drivers/irqchip/irq-imgpdc.c 	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
pdc_write         186 drivers/irqchip/irq-imgpdc.c 	pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
pdc_write         209 drivers/irqchip/irq-imgpdc.c 	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
pdc_write         277 drivers/irqchip/irq-imgpdc.c 	pdc_write(priv, PDC_IRQ_ENABLE, 0);
pdc_write         285 drivers/irqchip/irq-imgpdc.c 	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
pdc_write         293 drivers/irqchip/irq-imgpdc.c 		pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);