CQSPI_REG_CMDCTRL  339 drivers/mtd/spi-nor/cadence-quadspi.c 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
CQSPI_REG_CMDCTRL  342 drivers/mtd/spi-nor/cadence-quadspi.c 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
CQSPI_REG_CMDCTRL  345 drivers/mtd/spi-nor/cadence-quadspi.c 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,