CP_RB1_CNTL      2873 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
CP_RB1_CNTL      2874 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
CP_RB1_CNTL      1633 drivers/gpu/drm/radeon/ni.c 		CP_RB1_CNTL,
CP_RB1_CNTL      3705 drivers/gpu/drm/radeon/si.c 	WREG32(CP_RB1_CNTL, tmp);
CP_RB1_CNTL      3708 drivers/gpu/drm/radeon/si.c 	WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
CP_RB1_CNTL      3717 drivers/gpu/drm/radeon/si.c 	WREG32(CP_RB1_CNTL, tmp);