CP_RB0_CNTL      2832 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
CP_RB0_CNTL      2833 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
CP_RB0_CNTL      2835 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
CP_RB0_CNTL      4307 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
CP_RB0_CNTL      4308 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
CP_RB0_CNTL      4309 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
CP_RB0_CNTL      4310 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
CP_RB0_CNTL      4312 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
CP_RB0_CNTL      3215 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
CP_RB0_CNTL      3216 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
CP_RB0_CNTL      3218 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
CP_RB0_CNTL      4088 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_RB0_CNTL, tmp);
CP_RB0_CNTL      4091 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
CP_RB0_CNTL      4106 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_RB0_CNTL, tmp);
CP_RB0_CNTL      1632 drivers/gpu/drm/radeon/ni.c 		CP_RB0_CNTL,
CP_RB0_CNTL      3674 drivers/gpu/drm/radeon/si.c 	WREG32(CP_RB0_CNTL, tmp);
CP_RB0_CNTL      3677 drivers/gpu/drm/radeon/si.c 	WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
CP_RB0_CNTL      3693 drivers/gpu/drm/radeon/si.c 	WREG32(CP_RB0_CNTL, tmp);