CP_ME_CNTL       2439 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
CP_ME_CNTL       2440 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
CP_ME_CNTL       2441 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
CP_ME_CNTL       4151 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
CP_ME_CNTL       4152 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
CP_ME_CNTL       4153 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
CP_ME_CNTL       4155 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
CP_ME_CNTL       4156 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
CP_ME_CNTL       4157 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
CP_ME_CNTL       3069 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
CP_ME_CNTL       3070 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
CP_ME_CNTL       3071 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
CP_ME_CNTL       3880 drivers/gpu/drm/radeon/cik.c 		WREG32(CP_ME_CNTL, 0);
CP_ME_CNTL       3884 drivers/gpu/drm/radeon/cik.c 		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
CP_ME_CNTL       4961 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
CP_ME_CNTL       5165 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
CP_ME_CNTL       3018 drivers/gpu/drm/radeon/evergreen.c 	WREG32(CP_ME_CNTL, cp_me);
CP_ME_CNTL       3909 drivers/gpu/drm/radeon/evergreen.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
CP_ME_CNTL       4019 drivers/gpu/drm/radeon/evergreen.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
CP_ME_CNTL       1464 drivers/gpu/drm/radeon/ni.c 		WREG32(CP_ME_CNTL, 0);
CP_ME_CNTL       1468 drivers/gpu/drm/radeon/ni.c 		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
CP_ME_CNTL       1846 drivers/gpu/drm/radeon/ni.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
CP_ME_CNTL       1087 drivers/gpu/drm/radeon/rv770.c 	WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
CP_ME_CNTL       3467 drivers/gpu/drm/radeon/si.c 		WREG32(CP_ME_CNTL, 0);
CP_ME_CNTL       3471 drivers/gpu/drm/radeon/si.c 		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
CP_ME_CNTL       3880 drivers/gpu/drm/radeon/si.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
CP_ME_CNTL       4049 drivers/gpu/drm/radeon/si.c 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);