CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK  301 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK  298 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK  255 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK  221 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 3244 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 3249 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 4710 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 4715 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 4761 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 4766 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 6582 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 6587 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;