CP_INT_CNTL_RING0 1776 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
CP_INT_CNTL_RING0 1778 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
CP_INT_CNTL_RING0 1780 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
CP_INT_CNTL_RING0 1782 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
CP_INT_CNTL_RING0 4880 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 4886 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5033 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5052 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 3910 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 3911 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 3912 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 3913 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 6540 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
CP_INT_CNTL_RING0 6600 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
CP_INT_CNTL_RING0 6611 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
CP_INT_CNTL_RING0 6677 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
CP_INT_CNTL_RING0 2589 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 2590 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 2591 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 2592 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
CP_INT_CNTL_RING0 5485 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5555 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5574 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5599 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5608 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
CP_INT_CNTL_RING0 5775 drivers/gpu/drm/radeon/cik.c 	u32 tmp = RREG32(CP_INT_CNTL_RING0);
CP_INT_CNTL_RING0 5781 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_INT_CNTL_RING0, tmp);
CP_INT_CNTL_RING0 6874 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(CP_INT_CNTL_RING0) &
CP_INT_CNTL_RING0 6876 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_INT_CNTL_RING0, tmp);
CP_INT_CNTL_RING0 7052 drivers/gpu/drm/radeon/cik.c 	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
CP_INT_CNTL_RING0 7232 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
CP_INT_CNTL_RING0 5148 drivers/gpu/drm/radeon/si.c 	u32 tmp = RREG32(CP_INT_CNTL_RING0);
CP_INT_CNTL_RING0 5156 drivers/gpu/drm/radeon/si.c 	WREG32(CP_INT_CNTL_RING0, tmp);
CP_INT_CNTL_RING0 5953 drivers/gpu/drm/radeon/si.c 	tmp = RREG32(CP_INT_CNTL_RING0) &
CP_INT_CNTL_RING0 5955 drivers/gpu/drm/radeon/si.c 	WREG32(CP_INT_CNTL_RING0, tmp);
CP_INT_CNTL_RING0 6071 drivers/gpu/drm/radeon/si.c 	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
CP_INT_CNTL_RING0 6103 drivers/gpu/drm/radeon/si.c 	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);