CP_HQD_PQ_CONTROL  420 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 					   CP_HQD_PQ_CONTROL, QUEUE_SIZE);
CP_HQD_PQ_CONTROL  321 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 					   CP_HQD_PQ_CONTROL, QUEUE_SIZE);
CP_HQD_PQ_CONTROL 3328 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
CP_HQD_PQ_CONTROL 3330 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
CP_HQD_PQ_CONTROL 3333 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
CP_HQD_PQ_CONTROL 3335 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
CP_HQD_PQ_CONTROL 3336 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
CP_HQD_PQ_CONTROL 3337 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
CP_HQD_PQ_CONTROL 3338 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
CP_HQD_PQ_CONTROL 4510 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
CP_HQD_PQ_CONTROL 4512 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
CP_HQD_PQ_CONTROL 4515 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
CP_HQD_PQ_CONTROL 4517 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
CP_HQD_PQ_CONTROL 4518 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
CP_HQD_PQ_CONTROL 4519 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
CP_HQD_PQ_CONTROL 4520 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
CP_HQD_PQ_CONTROL 3489 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
CP_HQD_PQ_CONTROL 3491 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
CP_HQD_PQ_CONTROL 3494 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
CP_HQD_PQ_CONTROL 3496 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
CP_HQD_PQ_CONTROL 3497 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
CP_HQD_PQ_CONTROL 3498 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
CP_HQD_PQ_CONTROL 3499 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
CP_HQD_PQ_CONTROL 4672 drivers/gpu/drm/radeon/cik.c 		mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
CP_HQD_PQ_CONTROL 4687 drivers/gpu/drm/radeon/cik.c 		WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);