out_be64          167 arch/powerpc/include/asm/io.h DEF_MMIO_OUT_D(out_be64, 64, std);
out_be64          178 arch/powerpc/include/asm/io.h 	out_be64(addr, swab64(val));
out_be64          493 arch/powerpc/include/asm/io.h #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
out_be64          144 arch/powerpc/kvm/book3s_xive.c 	out_be64(xd->trig_mmio, 0);
out_be64          252 arch/powerpc/platforms/85xx/smp.c 	out_be64((u64 *)(&spin_table->addr_h),
out_be64          134 arch/powerpc/platforms/cell/cbe_thermal.c 	out_be64(&pmd_regs->tm_tpr.val, reg_value);
out_be64          354 arch/powerpc/platforms/cell/cbe_thermal.c 		out_be64(&pmd_regs->tm_str2, str2);
out_be64          355 arch/powerpc/platforms/cell/cbe_thermal.c 		out_be64(&pmd_regs->tm_str1.val, str1.val);
out_be64          356 arch/powerpc/platforms/cell/cbe_thermal.c 		out_be64(&pmd_regs->tm_tpr.val, tpr.val);
out_be64          357 arch/powerpc/platforms/cell/cbe_thermal.c 		out_be64(&pmd_regs->tm_cr1.val, cr1.val);
out_be64          358 arch/powerpc/platforms/cell/cbe_thermal.c 		out_be64(&pmd_regs->tm_cr2, cr2);
out_be64           73 arch/powerpc/platforms/cell/interrupt.c 	out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
out_be64          106 arch/powerpc/platforms/cell/interrupt.c 			out_be64(&node_iic->iic_is, ack);
out_be64          119 arch/powerpc/platforms/cell/interrupt.c 			out_be64(&node_iic->iic_is, ack);
out_be64          154 arch/powerpc/platforms/cell/interrupt.c 	out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
out_be64          174 arch/powerpc/platforms/cell/interrupt.c 	out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
out_be64          291 arch/powerpc/platforms/cell/interrupt.c 	out_be64(&iic->regs->prio, 0);
out_be64          344 arch/powerpc/platforms/cell/interrupt.c 		out_be64(&node_iic->iic_ir,
out_be64          351 arch/powerpc/platforms/cell/interrupt.c 		out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
out_be64          392 arch/powerpc/platforms/cell/interrupt.c 	out_be64(&iic_regs->iic_ir, iic_ir);
out_be64          145 arch/powerpc/platforms/cell/iommu.c 		out_be64(reg, val);
out_be64          251 arch/powerpc/platforms/cell/iommu.c 	out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
out_be64          394 arch/powerpc/platforms/cell/iommu.c 	out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
out_be64          396 arch/powerpc/platforms/cell/iommu.c 	out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
out_be64          408 arch/powerpc/platforms/cell/iommu.c 	out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
out_be64          413 arch/powerpc/platforms/cell/iommu.c 	out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
out_be64          698 arch/powerpc/platforms/cell/iommu.c 		out_be64(xregs + IOC_IOST_Origin, 0);
out_be64          702 arch/powerpc/platforms/cell/iommu.c 		out_be64(cregs + IOC_IOCmd_Cfg, val);
out_be64          118 arch/powerpc/platforms/cell/pervasive.c 		out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
out_be64           38 arch/powerpc/platforms/cell/pmu.c 		out_be64(&(pmd_regs->reg), (((u64)_x) << 32));	\
out_be64          289 arch/powerpc/platforms/cell/ras.c 			out_be64(&regs->ras_esc_0, 0);
out_be64           73 arch/powerpc/platforms/cell/spu_base.c 		out_be64(&priv2->slb_invalidate_all_W, 0UL);
out_be64          128 arch/powerpc/platforms/cell/spu_base.c 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
out_be64          142 arch/powerpc/platforms/cell/spu_base.c 	out_be64(&priv2->slb_index_W, slbe);
out_be64          144 arch/powerpc/platforms/cell/spu_base.c 	out_be64(&priv2->slb_esid_RW, 0);
out_be64          146 arch/powerpc/platforms/cell/spu_base.c 	out_be64(&priv2->slb_vsid_RW, slb->vsid);
out_be64          148 arch/powerpc/platforms/cell/spu_base.c 	out_be64(&priv2->slb_esid_RW, slb->esid);
out_be64          462 arch/powerpc/platforms/cell/spu_base.c 		out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
out_be64          464 arch/powerpc/platforms/cell/spu_base.c 			out_be64(&priv2->spu_chnldata_RW, 0);
out_be64          469 arch/powerpc/platforms/cell/spu_base.c 		out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
out_be64          470 arch/powerpc/platforms/cell/spu_base.c 		out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
out_be64           32 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
out_be64           40 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
out_be64           45 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_mask_RW[class], mask);
out_be64           55 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_stat_RW[class], stat);
out_be64           78 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_route_RW, route);
out_be64           93 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
out_be64           98 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
out_be64          103 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_sr1_RW, sr1);
out_be64          113 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
out_be64          123 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
out_be64          128 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
out_be64          138 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
out_be64          146 arch/powerpc/platforms/cell/spufs/hw_ops.c 	out_be64(&priv2->spu_cfg_RW, tmp);
out_be64          167 arch/powerpc/platforms/cell/spufs/hw_ops.c 	out_be64(&priv2->spu_cfg_RW, tmp);
out_be64          198 arch/powerpc/platforms/cell/spufs/hw_ops.c 	out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
out_be64          282 arch/powerpc/platforms/cell/spufs/hw_ops.c 	out_be64(&prob->mfc_ea_W, cmd->ea);
out_be64          305 arch/powerpc/platforms/cell/spufs/hw_ops.c 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
out_be64          109 arch/powerpc/platforms/cell/spufs/run.c 	out_be64(mfc_cntl, MFC_CNTL_PURGE_DMA_REQUEST);
out_be64          122 arch/powerpc/platforms/cell/spufs/run.c 	out_be64(mfc_cntl, 0);
out_be64          188 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
out_be64          271 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW,
out_be64          303 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&prob->spc_mssync_RW, 1UL);
out_be64          464 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW,
out_be64          529 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_privcntl_RW, 0UL);
out_be64          551 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
out_be64          625 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcntptr_RW, 1);
out_be64          631 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64          635 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnldata_RW, 0UL);
out_be64          636 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, 0UL);
out_be64          649 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
out_be64          655 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcnt_RW, 0UL);
out_be64          666 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
out_be64          685 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64          687 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
out_be64          700 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
out_be64          783 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&prob->mfc_ea_W, ea);
out_be64          784 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&prob->mfc_union_W.all64, command.all64);
out_be64          970 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
out_be64         1076 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcntptr_RW, 1);
out_be64         1077 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnldata_RW, 0UL);
out_be64         1082 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64         1084 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnldata_RW, 0UL);
out_be64         1085 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, 0UL);
out_be64         1103 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64         1105 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
out_be64         1317 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
out_be64         1392 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
out_be64         1427 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->puq[i].mfc_cq_data0_RW,
out_be64         1429 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->puq[i].mfc_cq_data1_RW,
out_be64         1431 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->puq[i].mfc_cq_data2_RW,
out_be64         1433 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->puq[i].mfc_cq_data3_RW,
out_be64         1437 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
out_be64         1439 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
out_be64         1441 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
out_be64         1443 arch/powerpc/platforms/cell/spufs/switch.c 			out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
out_be64         1479 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_tag_status_query_RW,
out_be64         1492 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
out_be64         1493 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
out_be64         1504 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
out_be64         1568 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64         1570 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
out_be64         1571 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
out_be64         1592 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64         1594 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
out_be64         1606 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
out_be64         1617 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
out_be64         1648 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
out_be64         1650 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
out_be64         1652 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
out_be64         1734 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
out_be64         1888 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_privcntl_RW, 4LL);
out_be64         1896 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
out_be64          165 arch/powerpc/platforms/powernv/eeh-powernv.c 	out_be64(phb->regs + offset, val);
out_be64          427 arch/powerpc/platforms/powernv/vas.h 	out_be64(regptr, val);
out_be64          438 arch/powerpc/platforms/powernv/vas.h 	out_be64(regptr, val);
out_be64          220 arch/powerpc/sysdev/xive/common.c 		out_be64(xd->eoi_mmio + offset, data);
out_be64          393 arch/powerpc/sysdev/xive/common.c 				out_be64(xd->trig_mmio, 0);
out_be64         1087 arch/powerpc/sysdev/xive/common.c 	out_be64(xd->trig_mmio, 0);
out_be64           59 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	out_be64(&mic_tm_regs->slow_fast_timer_0, MIC_Slow_Fast_Timer_table[pmode]);
out_be64           60 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	out_be64(&mic_tm_regs->slow_fast_timer_1, MIC_Slow_Fast_Timer_table[pmode]);
out_be64           62 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	out_be64(&mic_tm_regs->slow_next_timer_0, MIC_Slow_Next_Timer_table[pmode]);
out_be64           63 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	out_be64(&mic_tm_regs->slow_next_timer_1, MIC_Slow_Next_Timer_table[pmode]);
out_be64           71 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	out_be64(&pmd_regs->pmcr, value);
out_be64          204 drivers/dma/fsldma.h #define fsl_iowrite64be(v, p)	out_be64(p, v)
out_be64          117 drivers/edac/cell_edac.c 		out_be64(&priv->regs->mic_fir, fir);
out_be64          783 drivers/misc/cxl/cxl.h 		out_be64(_cxl_p1_addr(cxl, reg), val);
out_be64          803 drivers/misc/cxl/cxl.h 		out_be64(_cxl_p1n_addr(afu, reg), val);
out_be64          822 drivers/misc/cxl/cxl.h 		out_be64(_cxl_p2n_addr(afu, reg), val);
out_be64           23 drivers/misc/cxl/debugfs.c 	out_be64((u64 __iomem *)data, val);
out_be64          124 drivers/misc/ocxl/link.c 		out_be64(spa->reg_tfc, reg);