or 181 arch/alpha/include/asm/atomic.h ATOMIC_OPS(or, bis) or 197 arch/arc/include/asm/atomic.h ATOMIC_OPS(or, |=, or) or 297 arch/arc/include/asm/atomic.h ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3) or 436 arch/arc/include/asm/atomic.h ATOMIC64_OPS(or, or, or) or 260 arch/arc/include/asm/entry-arcv2.h or r9, r9, STATUS_IE_MASK or 116 arch/arc/include/asm/entry-compact.h or r9, r9, (STATUS_E1_MASK|STATUS_E2_MASK) or 188 arch/arc/include/asm/irqflags-compact.h or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK) or 38 arch/arc/include/asm/tlb-mmu1.h or.nz r0,r0,1 ; set way bit or 59 arch/arc/include/asm/tlb-mmu1.h or r0,r0,r1 /* Instruction address + Data ASID */ or 237 arch/arm/include/asm/atomic.h ATOMIC_OPS(or, |=, orr) or 393 arch/arm/include/asm/atomic.h ATOMIC64_OPS(or, orr, orr) or 123 arch/arm64/include/asm/atomic_ll_sc.h ATOMIC_OPS(or, orr, K) or 222 arch/arm64/include/asm/atomic_ll_sc.h ATOMIC64_OPS(or, orr, L) or 24 arch/arm64/include/asm/atomic_lse.h ATOMIC_OP(or, stset) or 50 arch/arm64/include/asm/atomic_lse.h ATOMIC_FETCH_OPS(or, ldset) or 177 arch/arm64/include/asm/atomic_lse.h ATOMIC64_OP(or, stset) or 203 arch/arm64/include/asm/atomic_lse.h ATOMIC64_FETCH_OPS(or, ldset) or 114 arch/arm64/include/asm/percpu.h PERCPU_OP(or, orr, stset) or 210 arch/csky/abiv2/inc/abi/entry.h or r8, r7 or 213 arch/csky/abiv2/inc/abi/entry.h or r8, r7 or 195 arch/csky/include/asm/atomic.h ATOMIC_FETCH_OP(or, |) or 202 arch/csky/include/asm/atomic.h ATOMIC_OP(or, |) or 63 arch/h8300/include/asm/atomic.h ATOMIC_OPS(or, |=) or 144 arch/hexagon/include/asm/atomic.h ATOMIC_OPS(or) or 111 arch/ia64/include/asm/atomic.h ATOMIC_FETCH_OP(or, |) or 196 arch/ia64/include/asm/atomic.h ATOMIC64_FETCH_OP(or, |) or 57 arch/m68k/fpsp040/fpsp.h | handled by the package, or "bra real_xxxx" which is an external or 163 arch/m68k/fpsp040/fpsp.h .set denorm_bit,7 | bit determines if denorm or unnorm or 1220 arch/m68k/ifpsp060/src/fpsp.S # if the exception is an opclass zero or two unimplemented data type or 3294 arch/m68k/ifpsp060/src/fpsp.S # if the effective addressing mode was -() or ()+, then the address # or 12203 arch/m68k/ifpsp060/src/fpsp.S # if underflow or inexact is enabled, then go calculate the EXOP first. or 12983 arch/m68k/ifpsp060/src/fpsp.S # if underflow or inexact is enabled, go calculate EXOP first. or 13599 arch/m68k/ifpsp060/src/fpsp.S # if underflow or inexact is enabled, go calculate EXOP first. or 15679 arch/m68k/ifpsp060/src/fpsp.S # if underflow or inexact is enabled, go calculate EXOP first. or 18080 arch/m68k/ifpsp060/src/fpsp.S # if the addressing mode is post-increment or pre-decrement, or 19789 arch/m68k/ifpsp060/src/fpsp.S # if the ea is -() or ()+, need to know # of bytes. # or 23499 arch/m68k/ifpsp060/src/fpsp.S # if it is a positive number, or the number of digits # or 24713 arch/m68k/ifpsp060/src/fpsp.S # if the effective addressing mode was predecrement or postincrement, or 1219 arch/m68k/ifpsp060/src/pfpsp.S # if the exception is an opclass zero or two unimplemented data type or 3293 arch/m68k/ifpsp060/src/pfpsp.S # if the effective addressing mode was -() or ()+, then the address # or 8634 arch/m68k/ifpsp060/src/pfpsp.S # if underflow or inexact is enabled, then go calculate the EXOP first. or 9414 arch/m68k/ifpsp060/src/pfpsp.S # if underflow or inexact is enabled, go calculate EXOP first. or 10030 arch/m68k/ifpsp060/src/pfpsp.S # if underflow or inexact is enabled, go calculate EXOP first. or 12110 arch/m68k/ifpsp060/src/pfpsp.S # if underflow or inexact is enabled, go calculate EXOP first. or 13459 arch/m68k/ifpsp060/src/pfpsp.S # if it is a positive number, or the number of digits # or 14673 arch/m68k/ifpsp060/src/pfpsp.S # if the effective addressing mode was predecrement or postincrement, or 117 arch/m68k/include/asm/atomic.h ATOMIC_OPS(or, |=, or) or 97 arch/m68k/math-emu/fp_decode.h | either source fp register or data format or 188 arch/m68k/math-emu/fp_decode.h | get the extension word and test for brief or full extension type or 356 arch/m68k/math-emu/fp_decode.h | with base and/or outer displacement or 167 arch/mips/include/asm/atomic.h ATOMIC_OPS(or, |=, or) or 369 arch/mips/include/asm/atomic.h ATOMIC64_OPS(or, |=, or) or 38 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h or v0, v0, 0x5001 or 64 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h or v0, v0, 0x2000 # Set IPREF bit. or 82 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h # OCTEON II or better have bit 15 set. Clear the error bits. or 49 arch/mips/include/asm/mach-ip27/kernel-entry-init.h or t1, t1, t0 # Physical load address of kernel text or 50 arch/mips/include/asm/mach-ip27/kernel-entry-init.h or t2, t2, t0 # Physical load address of kernel data or 56 arch/mips/include/asm/mach-ip27/kernel-entry-init.h or t0, t0, t1 or 59 arch/mips/include/asm/mach-ip27/kernel-entry-init.h or t0, t0, t2 or 91 arch/mips/include/asm/mach-ip27/kernel-entry-init.h or t0, t0, t1 or 25 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h or t0, (0x1 << 7) or 29 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h or t0, (0x1 << 29) or 37 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h or t0, 0x100 or 54 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h or t0, (0x1 << 7) or 58 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h or t0, (0x1 << 29) or 66 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h or t0, 0x100 or 58 arch/mips/include/asm/mach-malta/kernel-entry-init.h or t0, t2 or 79 arch/mips/include/asm/mach-malta/kernel-entry-init.h or t0, t2 or 85 arch/mips/include/asm/mach-malta/kernel-entry-init.h or t0, t0, t2 or 367 arch/mips/include/asm/stackframe.h or v0, a0 or 405 arch/mips/include/asm/stackframe.h or v0, a0 or 454 arch/mips/include/asm/stackframe.h or t0, t1 or 467 arch/mips/include/asm/stackframe.h or t0, t1 or 484 arch/mips/include/asm/stackframe.h or t0, t2 or 486 arch/mips/include/asm/stackframe.h or t0, t1 or 540 arch/mips/net/ebpf_jit.c emit_instr(ctx, or, dst, dst, MIPS_R_AT); or 863 arch/mips/net/ebpf_jit.c emit_instr(ctx, or, dst, dst, src); or 955 arch/mips/net/ebpf_jit.c emit_instr(ctx, or, dst, dst, src); or 1084 arch/mips/net/ebpf_jit.c emit_instr(ctx, or, MIPS_R_AT, MIPS_R_T9, MIPS_R_AT); or 75 arch/openrisc/include/asm/atomic.h ATOMIC_FETCH_OP(or) or 79 arch/openrisc/include/asm/atomic.h ATOMIC_OP(or) or 131 arch/parisc/include/asm/atomic.h ATOMIC_OPS(or, |=) or 196 arch/parisc/include/asm/atomic.h ATOMIC64_OPS(or, |=) or 114 arch/powerpc/include/asm/atomic.h ATOMIC_OPS(or, or) or 385 arch/powerpc/include/asm/atomic.h ATOMIC64_OPS(or, or) or 84 arch/powerpc/include/asm/bitops.h DEFINE_BITOP(set_bits, or, "") or 132 arch/powerpc/include/asm/bitops.h DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER, or 134 arch/powerpc/include/asm/bitops.h DEFINE_TESTOP(test_and_set_bits_lock, or, "", or 48 arch/powerpc/include/asm/fsl_lbc.h __be32 or; /**< Base Register */ or 166 arch/powerpc/include/asm/ppc_asm.h #define HMT_VERY_LOW or 31,31,31 # very low priority or 167 arch/powerpc/include/asm/ppc_asm.h #define HMT_LOW or 1,1,1 or 168 arch/powerpc/include/asm/ppc_asm.h #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority or 169 arch/powerpc/include/asm/ppc_asm.h #define HMT_MEDIUM or 2,2,2 or 170 arch/powerpc/include/asm/ppc_asm.h #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority or 171 arch/powerpc/include/asm/ppc_asm.h #define HMT_HIGH or 3,3,3 or 172 arch/powerpc/include/asm/ppc_asm.h #define HMT_EXTRA_HIGH or 7,7,7 # power7 only or 27 arch/powerpc/platforms/4xx/gpio.c __be32 or; or 73 arch/powerpc/platforms/4xx/gpio.c setbits32(®s->or, GPIO_MASK(gpio)); or 75 arch/powerpc/platforms/4xx/gpio.c clrbits32(®s->or, GPIO_MASK(gpio)); or 235 arch/powerpc/platforms/85xx/p1022_ds.c or0 = in_be32(&lbc->bank[0].or); or 236 arch/powerpc/platforms/85xx/p1022_ds.c or1 = in_be32(&lbc->bank[1].or); or 253 arch/powerpc/platforms/85xx/p1022_ds.c out_be32(&lbc->bank[0].or, or0); or 259 arch/powerpc/platforms/85xx/p1022_ds.c out_be32(&lbc->bank[1].or, or1); or 75 arch/powerpc/sysdev/fsl_lbc.c u32 or = in_be32(&lbc->bank[i].or); or 77 arch/powerpc/sysdev/fsl_lbc.c if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base)) or 79 arch/riscv/include/asm/atomic.h ATOMIC_OPS( or, or, i) or 177 arch/riscv/include/asm/atomic.h ATOMIC_OPS( or, or, i) or 74 arch/riscv/include/asm/bitops.h return __test_and_op_bit(or, __NOP, nr, addr); or 116 arch/riscv/include/asm/bitops.h __op_bit(or, __NOP, nr, addr); or 158 arch/riscv/include/asm/bitops.h return __test_and_op_bit_ord(or, __NOP, nr, addr, .aq); or 73 arch/s390/include/asm/atomic.h ATOMIC_OPS(or) or 143 arch/s390/include/asm/atomic.h ATOMIC64_OPS(or) or 153 arch/sh/drivers/dma/dmabrg.c unsigned long or; or 173 arch/sh/drivers/dma/dmabrg.c or = __raw_readl(DMAOR); or 174 arch/sh/drivers/dma/dmabrg.c __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR); or 78 arch/sh/include/asm/atomic-grb.h ATOMIC_OPS(or) or 64 arch/sh/include/asm/atomic-irq.h ATOMIC_OPS(or, |=) or 80 arch/sh/include/asm/atomic-llsc.h ATOMIC_OPS(or) or 45 arch/sparc/include/asm/atomic_64.h ATOMIC_OPS(or) or 36 arch/sparc/include/asm/head_32.h or %l7, %lo(sys_call_table), %l7; \ or 45 arch/sparc/include/asm/head_64.h or %tmp2, %lo(__CHEETAH_ID), %tmp2;\ or 54 arch/sparc/include/asm/head_64.h or %tmp2, %lo(__JALAPENO_ID), %tmp2;\ or 140 arch/sparc/include/asm/trap_block.h or REG, 0xd0, REG; \ or 155 arch/sparc/include/asm/trap_block.h or DEST, %lo(trap_block), DEST; \ or 186 arch/sparc/include/asm/trap_block.h or REG2, %lo(trap_block), REG2; \ or 194 arch/sparc/include/asm/trap_block.h or DEST, %lo(trap_block), DEST; \ or 158 arch/sparc/include/asm/tsb.h or REG1, %lo(swapper_pg_dir), REG1; \ or 190 arch/sparc/include/asm/tsb.h or REG1, REG2, REG1; \ or 226 arch/sparc/include/asm/tsb.h or REG1, REG2, REG1; \ or 254 arch/sparc/include/asm/tsb.h or REG1, REG2, REG1; \ or 304 arch/sparc/include/asm/tsb.h or REG1, %lo(prom_trans), REG1; \ or 341 arch/sparc/include/asm/tsb.h or REG1, %ulo(swapper_tsb), REG1; \ or 342 arch/sparc/include/asm/tsb.h or REG2, %lo(swapper_tsb), REG2; \ or 347 arch/sparc/include/asm/tsb.h or REG1, REG2, REG1; \ or 364 arch/sparc/include/asm/tsb.h or REG1, %ulo(swapper_4m_tsb), REG1; \ or 365 arch/sparc/include/asm/tsb.h or REG2, %lo(swapper_4m_tsb), REG2; \ or 370 arch/sparc/include/asm/tsb.h or REG1, REG2, REG1; \ or 28 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 38 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 47 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 67 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 77 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 87 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 99 arch/sparc/include/asm/ttable.h 109: or %g7, %lo(109b), %g7; \ or 102 arch/sparc/include/asm/ttable.h or %l7, %lo(systbl), %l7; or 131 arch/sparc/include/asm/ttable.h or %g7, %lo(1f-4), %g7; \ or 22 arch/sparc/include/asm/visasm.h or %g7, %lo(297f), %g7; \ or 124 arch/sparc/include/asm/winmacro.h or %dest_reg, %lo(current_set), %dest_reg;\ or 64 arch/sparc/lib/atomic32.c ATOMIC_FETCH_OP(or, |=) or 43 arch/unicore32/include/asm/assembler.h or \temp, \temp, #PSR_I_BIT | PRIV_MODE or 50 arch/unicore32/include/asm/assembler.h or \temp, \temp, #PRIV_MODE or 991 arch/x86/kvm/emulate.c FASTOP2(or); or 250 arch/xtensa/include/asm/atomic.h ATOMIC_OPS(or) or 210 arch/xtensa/include/asm/initialize_mmu.h or a9, a9, a6 or 313 drivers/dma/ti/edma.c unsigned or) or 318 drivers/dma/ti/edma.c val |= or; or 330 drivers/dma/ti/edma.c static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) or 334 drivers/dma/ti/edma.c val |= or; or 351 drivers/dma/ti/edma.c unsigned and, unsigned or) or 353 drivers/dma/ti/edma.c edma_modify(ecc, offset + (i << 2), and, or); or 357 drivers/dma/ti/edma.c unsigned or) or 359 drivers/dma/ti/edma.c edma_or(ecc, offset + (i << 2), or); or 363 drivers/dma/ti/edma.c unsigned or) or 365 drivers/dma/ti/edma.c edma_or(ecc, offset + ((i * 2 + j) << 2), or); or 410 drivers/dma/ti/edma.c int param_no, unsigned and, unsigned or) or 412 drivers/dma/ti/edma.c edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); or 422 drivers/dma/ti/edma.c unsigned or) or 424 drivers/dma/ti/edma.c edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); or 1097 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) or 202 drivers/gpu/drm/drm_crtc_internal.h int drm_mode_addfb(struct drm_device *dev, struct drm_mode_fb_cmd *or, or 116 drivers/gpu/drm/drm_framebuffer.c int drm_mode_addfb(struct drm_device *dev, struct drm_mode_fb_cmd *or, or 125 drivers/gpu/drm/drm_framebuffer.c r.pixel_format = drm_driver_legacy_fb_format(dev, or->bpp, or->depth); or 127 drivers/gpu/drm/drm_framebuffer.c DRM_DEBUG("bad {bpp:%d, depth:%d}\n", or->bpp, or->depth); or 132 drivers/gpu/drm/drm_framebuffer.c r.fb_id = or->fb_id; or 133 drivers/gpu/drm/drm_framebuffer.c r.width = or->width; or 134 drivers/gpu/drm/drm_framebuffer.c r.height = or->height; or 135 drivers/gpu/drm/drm_framebuffer.c r.pitches[0] = or->pitch; or 136 drivers/gpu/drm/drm_framebuffer.c r.handles[0] = or->handle; or 142 drivers/gpu/drm/drm_framebuffer.c or->fb_id = r.fb_id; or 92 drivers/gpu/drm/msm/adreno/a6xx_gmu.h static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) or 98 drivers/gpu/drm/msm/adreno/a6xx_gmu.h gmu_write(gmu, reg, val | or); or 372 drivers/gpu/drm/msm/msm_gem_submit.c ptr[off] = iova | submit_reloc.or; or 224 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) or 229 drivers/gpu/drm/msm/msm_gpu.h gpu_write(gpu, reg, val | or); or 45 drivers/gpu/drm/nouveau/dispnv04/dac.c if (dcb->or & (8 | DCB_OUTPUT_C)) or 47 drivers/gpu/drm/nouveau/dispnv04/dac.c if (dcb->or & (8 | DCB_OUTPUT_B)) or 346 drivers/gpu/drm/nouveau/dispnv04/dac.c '@' + ffs(dcb->or)); or 422 drivers/gpu/drm/nouveau/dispnv04/dac.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); or 431 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1]; or 456 drivers/gpu/drm/nouveau/dispnv04/dac.c (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index)); or 541 drivers/gpu/drm/nouveau/dispnv04/dac.c nv_encoder->or = ffs(entry->or) - 1; or 61 drivers/gpu/drm/nouveau/dispnv04/dfp.c int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; or 78 drivers/gpu/drm/nouveau/dispnv04/dfp.c int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; or 87 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); or 90 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); or 207 drivers/gpu/drm/nouveau/dispnv04/dfp.c uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000; or 264 drivers/gpu/drm/nouveau/dispnv04/dfp.c *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30; or 482 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); or 707 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_encoder->or = ffs(entry->or) - 1; or 100 drivers/gpu/drm/nouveau/dispnv04/hw.h int or, int dl, uint8_t address) or 102 drivers/gpu/drm/nouveau/dispnv04/hw.h int ramdac = (or & DCB_OUTPUT_C) >> 2; or 110 drivers/gpu/drm/nouveau/dispnv04/hw.h int or, int dl, uint8_t address, or 113 drivers/gpu/drm/nouveau/dispnv04/hw.h int ramdac = (or & DCB_OUTPUT_C) >> 2; or 176 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); or 235 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c nv_encoder->or = ffs(entry->or) - 1; or 193 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c '@' + ffs(dcb->or)); or 603 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); or 812 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->base.or = ffs(entry->or) - 1; or 118 drivers/gpu/drm/nouveau/dispnv50/atom.h } or; or 137 drivers/gpu/drm/nouveau/dispnv50/atom.h bool or:1; or 23 drivers/gpu/drm/nouveau/dispnv50/core.h void (*ctrl)(struct nv50_core *, int or, u32 ctrl, or 25 drivers/gpu/drm/nouveau/dispnv50/dac507d.c dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl, or 31 drivers/gpu/drm/nouveau/dispnv50/dac507d.c sync |= asyh->or.nvsync << 1; or 32 drivers/gpu/drm/nouveau/dispnv50/dac507d.c sync |= asyh->or.nhsync; or 34 drivers/gpu/drm/nouveau/dispnv50/dac507d.c evo_mthd(push, 0x0400 + (or * 0x080), 2); or 25 drivers/gpu/drm/nouveau/dispnv50/dac907d.c dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl, or 30 drivers/gpu/drm/nouveau/dispnv50/dac907d.c evo_mthd(push, 0x0180 + (or * 0x020), 1); or 273 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->or = -1; or 299 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->or = args.info.or; or 367 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.bpc = connector->display_info.bpc; or 381 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); or 396 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); or 397 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.depth = 0; or 808 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.bpc = min(connector->display_info.bpc, 8U); or 809 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3); or 873 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_dp_bpc_to_depth(armh->or.bpc)); or 1420 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.depth = depth; or 1423 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); or 1527 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->or.bpc == 8) or 1534 drivers/gpu/drm/nouveau/dispnv50/disp.c depth = nv50_dp_bpc_to_depth(asyh->or.bpc); or 1666 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); or 1685 drivers/gpu/drm/nouveau/dispnv50/disp.c switch (asyh->or.bpc) { or 1686 drivers/gpu/drm/nouveau/dispnv50/disp.c case 10: asyh->or.depth = 0x6; break; or 1687 drivers/gpu/drm/nouveau/dispnv50/disp.c case 8: asyh->or.depth = 0x5; break; or 1688 drivers/gpu/drm/nouveau/dispnv50/disp.c case 6: asyh->or.depth = 0x2; break; or 1689 drivers/gpu/drm/nouveau/dispnv50/disp.c default: asyh->or.depth = 0x0; break; or 1702 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); or 2408 drivers/gpu/drm/nouveau/dispnv50/disp.c ffs(dcbe->or) - 1, ret); or 63 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.or ) head->func->or (head, asyh); or 87 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->base.depth > asyh->or.bpc * 3) or 94 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->or.bpc >= 8) or 287 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); or 288 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); or 289 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.or = head->func->or != NULL; or 325 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.or = head->func->or != NULL; or 435 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->or = armh->or; or 40 drivers/gpu/drm/nouveau/dispnv50/head.h void (*or)(struct nv50_head *, struct nv50_head_atom *); or 32 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, 0x00000001 | asyh->or.depth << 6 | or 33 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->or.nvsync << 4 | or 34 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->or.nhsync << 3); or 301 drivers/gpu/drm/nouveau/dispnv50/head907d.c .or = head907d_or, or 99 drivers/gpu/drm/nouveau/dispnv50/head917d.c .or = head907d_or, or 35 drivers/gpu/drm/nouveau/dispnv50/headc37d.c switch (asyh->or.depth) { or 36 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 6: asyh->or.depth = 5; break; or 37 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 5: asyh->or.depth = 4; break; or 38 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 2: asyh->or.depth = 1; break; or 39 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 0: asyh->or.depth = 4; break; or 47 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->or.depth << 4 | or 48 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->or.nvsync << 3 | or 49 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->or.nhsync << 2); or 212 drivers/gpu/drm/nouveau/dispnv50/headc37d.c .or = headc37d_or, or 35 drivers/gpu/drm/nouveau/dispnv50/headc57d.c switch (asyh->or.depth) { or 36 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 6: asyh->or.depth = 5; break; or 37 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 5: asyh->or.depth = 4; break; or 38 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 2: asyh->or.depth = 1; break; or 39 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 0: asyh->or.depth = 4; break; or 47 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->or.depth << 4 | or 48 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->or.nvsync << 3 | or 49 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->or.nhsync << 2); or 205 drivers/gpu/drm/nouveau/dispnv50/headc57d.c .or = headc57d_or, or 25 drivers/gpu/drm/nouveau/dispnv50/pior507d.c pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl, or 31 drivers/gpu/drm/nouveau/dispnv50/pior507d.c ctrl |= asyh->or.depth << 16; or 32 drivers/gpu/drm/nouveau/dispnv50/pior507d.c ctrl |= asyh->or.nvsync << 13; or 33 drivers/gpu/drm/nouveau/dispnv50/pior507d.c ctrl |= asyh->or.nhsync << 12; or 35 drivers/gpu/drm/nouveau/dispnv50/pior507d.c evo_mthd(push, 0x0700 + (or * 0x040), 1); or 25 drivers/gpu/drm/nouveau/dispnv50/sor507d.c sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl, or 31 drivers/gpu/drm/nouveau/dispnv50/sor507d.c ctrl |= asyh->or.depth << 16; or 32 drivers/gpu/drm/nouveau/dispnv50/sor507d.c ctrl |= asyh->or.nvsync << 13; or 33 drivers/gpu/drm/nouveau/dispnv50/sor507d.c ctrl |= asyh->or.nhsync << 12; or 35 drivers/gpu/drm/nouveau/dispnv50/sor507d.c evo_mthd(push, 0x0600 + (or * 0x40), 1); or 27 drivers/gpu/drm/nouveau/dispnv50/sor907d.c sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl, or 32 drivers/gpu/drm/nouveau/dispnv50/sor907d.c evo_mthd(push, 0x0200 + (or * 0x20), 1); or 25 drivers/gpu/drm/nouveau/dispnv50/sorc37d.c sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl, or 30 drivers/gpu/drm/nouveau/dispnv50/sorc37d.c evo_mthd(push, 0x0300 + (or * 0x20), 1); or 47 drivers/gpu/drm/nouveau/include/nvif/cl5070.h __u8 or; or 26 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h uint8_t or; or 10 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h int or; or 26 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h .or = -1, \ or 121 drivers/gpu/drm/nouveau/nouveau_backlight.c int or = ffs(nv_encoder->dcb->or) - 1; or 125 drivers/gpu/drm/nouveau/nouveau_backlight.c val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); or 136 drivers/gpu/drm/nouveau/nouveau_backlight.c int or = ffs(nv_encoder->dcb->or) - 1; or 140 drivers/gpu/drm/nouveau/nouveau_backlight.c nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), or 157 drivers/gpu/drm/nouveau/nouveau_backlight.c int or = ffs(nv_encoder->dcb->or) - 1; or 160 drivers/gpu/drm/nouveau/nouveau_backlight.c div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); or 161 drivers/gpu/drm/nouveau/nouveau_backlight.c val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); or 175 drivers/gpu/drm/nouveau/nouveau_backlight.c int or = ffs(nv_encoder->dcb->or) - 1; or 178 drivers/gpu/drm/nouveau/nouveau_backlight.c div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); or 181 drivers/gpu/drm/nouveau/nouveau_backlight.c nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), or 205 drivers/gpu/drm/nouveau/nouveau_backlight.c if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1))) or 111 drivers/gpu/drm/nouveau/nouveau_bios.c uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0); or 128 drivers/gpu/drm/nouveau/nouveau_bios.c nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); or 148 drivers/gpu/drm/nouveau/nouveau_bios.c unsigned int outputset = (dcbent->or == 4) ? 1 : 0; or 169 drivers/gpu/drm/nouveau/nouveau_bios.c if (dcbent->or == 4) or 179 drivers/gpu/drm/nouveau/nouveau_bios.c int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; or 647 drivers/gpu/drm/nouveau/nouveau_bios.c switch (ffs(dcbent->or)) { or 1382 drivers/gpu/drm/nouveau/nouveau_bios.c int heads, int or) or 1391 drivers/gpu/drm/nouveau/nouveau_bios.c entry->or = or; or 1407 drivers/gpu/drm/nouveau/nouveau_bios.c entry->or = (conn >> 24) & 0xf; or 1526 drivers/gpu/drm/nouveau/nouveau_bios.c ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); or 1537 drivers/gpu/drm/nouveau/nouveau_bios.c entry->hashm = (entry->heads << 8) | (link << 6) | entry->or; or 1571 drivers/gpu/drm/nouveau/nouveau_bios.c entry->or = entry->heads; /* same as heads, hopefully safe enough */ or 1621 drivers/gpu/drm/nouveau/nouveau_bios.c jent->or == ient->or) { or 45 drivers/gpu/drm/nouveau/nouveau_encoder.h int or; or 409 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ior = nvkm_ior_find(disp, SOR, ffs(outp->info.or) - 1); or 255 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.or = ior->id; or 296 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.or = dp->outp.ior->id; or 308 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.or = dp->outp.ior->id; or 314 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.or = dp->outp.ior->id; or 322 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.or = dp->outp.ior->id; or 430 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.or = ior->id; or 464 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c datakbps += khz * head->asy.or.depth; or 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h } or; or 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c case 6: state->or.depth = 30; break; or 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c case 5: state->or.depth = 24; break; or 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c case 2: state->or.depth = 18; break; or 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c case 0: state->or.depth = 18; break; /*XXX: "default" */ or 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c state->or.depth = 18; or 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c case 5: state->or.depth = 30; break; or 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c case 4: state->or.depth = 24; break; or 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c case 1: state->or.depth = 18; break; or 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c state->or.depth = 18; or 189 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c const u16 m = (0x0100 << head->id) | (l << 6) | outp->info.or; or 221 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (head->asy.or.depth == 24) or 246 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c init.or = ior->id; or 271 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c init.or = ior->id; or 352 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c link_data_rate = (khz * head->asy.or.depth / 8) / ior->dp.nr; or 453 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c head->asy.or.depth = (disp->sor.lvdsconf & 0x0200) ? 24 : 18; or 134 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c ior = nvkm_ior_find(outp->disp, SOR, ffs(outp->info.or) - 1); or 152 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c (ior->func->route.set || ior->id == __ffs(outp->info.or))) or 161 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c (ior->func->route.set || ior->id == __ffs(outp->info.or))) or 204 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c id = ffs(outp->info.or) - 1; or 262 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c outp->info.type, outp->info.location, outp->info.or, or 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c case 6: state->or.depth = 30; break; or 85 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c case 5: state->or.depth = 24; break; or 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c case 2: state->or.depth = 18; break; or 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c case 0: state->or.depth = 18; break; /*XXX*/ or 89 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c state->or.depth = 18; or 104 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c args->v0.or = outp->ior->id; or 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c const u32 moff = __ffs(outp->info.or) * 0x100; or 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c for (*link = 0, m = __ffs(outp->info.or) * 2, s = 0; s < 2; m++, s++) { or 117 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c return (outp->heads << 8) | (outp->link << 6) | outp->or; or 129 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c outp->or = (conn & 0x0f000000) >> 24; or 92 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (init->or >= 0) or 93 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return init->or; or 556 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 dacoffset = pramdac_offset[init->outp->or]; or 817 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c (init->outp->or << 0) | or 852 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 or = init_or(init); or 855 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); or 859 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); or 871 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 or = init_or(init); or 874 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); or 878 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wrvgai(init, 0x03d4, index, data | (1 << or)); or 142 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c init.or = ffs(outp.or) - 1; or 2550 drivers/gpu/drm/radeon/radeon.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) or 1421 drivers/media/platform/s3c-camif/camif-capture.c struct v4l2_rect *or = &camif->vp[i].out_frame.rect; or 1422 drivers/media/platform/s3c-camif/camif-capture.c if ((or->width > r->width) == (or->height > r->height)) or 1047 drivers/misc/habanalabs/habanalabs.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) or 697 drivers/mtd/nand/raw/fsl_elbc_nand.c if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) or 812 drivers/mtd/nand/raw/fsl_elbc_nand.c clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); or 815 drivers/mtd/nand/raw/fsl_elbc_nand.c setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); or 878 drivers/mtd/nand/raw/fsl_elbc_nand.c in_be32(&lbc->bank[bank].or) & BR_BA) or 360 drivers/net/hamradio/scc.c or(scc,R3,ENT_HM|RxENABLE); /* enable the receiver, hunt mode */ or 402 drivers/net/hamradio/scc.c or(scc,R10,ABUNDER); /* re-install underrun protection */ or 506 drivers/net/hamradio/scc.c or(scc,R10,ABUNDER); or 525 drivers/net/hamradio/scc.c or(scc,R3,ENT_HM); /* enter hunt mode for next flag */ or 539 drivers/net/hamradio/scc.c or(scc, R3, ENT_HM); or 555 drivers/net/hamradio/scc.c or(scc, R3, ENT_HM); or 579 drivers/net/hamradio/scc.c or(scc,R3,ENT_HM); /* enter hunt mode for next flag */ or 724 drivers/net/hamradio/scc.c or(scc,R14,BRENABL); /* enable baudrate generator */ or 860 drivers/net/hamradio/scc.c or(scc,R15,SHDLCE|FIFOE); /* enable FIFO, SDLC/HDLC Enhancements (From now R7 is R7') */ or 877 drivers/net/hamradio/scc.c or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */ or 881 drivers/net/hamradio/scc.c or(scc,R9,MIE); /* master interrupt enable */ or 915 drivers/net/hamradio/scc.c or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */ or 916 drivers/net/hamradio/scc.c or(scc, R15, TxUIE); or 935 drivers/net/hamradio/scc.c or(scc,R5, TxENAB); or 938 drivers/net/hamradio/scc.c or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ or 952 drivers/net/hamradio/scc.c or(scc,R15, scc->kiss.softdcd? SYNCIE:DCDIE); or 969 drivers/net/hamradio/scc.c or(scc,R5, TxENAB); or 972 drivers/net/hamradio/scc.c or(scc,R5,RTS|TxENAB); /* enable tx */ or 984 drivers/net/hamradio/scc.c or(scc, R15, scc->kiss.softdcd? SYNCIE:DCDIE); or 1324 drivers/net/hamradio/scc.c or(scc, R15, SYNCIE); or 1328 drivers/net/hamradio/scc.c or(scc, R15, DCDIE); or 140 drivers/pinctrl/meson/pinctrl-meson.h #define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ or 152 drivers/pinctrl/meson/pinctrl-meson.h [REG_OUT] = { or, ob }, \ or 158 drivers/pinctrl/meson/pinctrl-meson.h #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ or 159 drivers/pinctrl/meson/pinctrl-meson.h BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) or 94 drivers/uio/uio_fsl_elbc_gpcm.c in_be32(&bank->or)); or 118 drivers/uio/uio_fsl_elbc_gpcm.c reg_or_cur = in_be32(&bank->or); or 140 drivers/uio/uio_fsl_elbc_gpcm.c out_be32(&bank->or, reg_new); or 348 drivers/uio/uio_fsl_elbc_gpcm.c reg_or_cur = in_be32(&priv->lbc->bank[priv->bank].or); or 378 drivers/uio/uio_fsl_elbc_gpcm.c out_be32(&priv->lbc->bank[priv->bank].or, reg_or_new); or 68 drivers/watchdog/rc32434_wdt.c #define SET_BITS(addr, or, nand) \ or 69 drivers/watchdog/rc32434_wdt.c writel((readl(&addr) | or) & ~nand, &addr) or 89 drivers/watchdog/rc32434_wdt.c u32 or, nand; or 99 drivers/watchdog/rc32434_wdt.c or = 1 << RC32434_ERR_WRE; or 104 drivers/watchdog/rc32434_wdt.c SET_BITS(wdt_reg->errcs, or, nand); or 111 drivers/watchdog/rc32434_wdt.c or = 1 << RC32434_WTC_EN; or 113 drivers/watchdog/rc32434_wdt.c SET_BITS(wdt_reg->wtc, or, nand); or 902 fs/ocfs2/dlmglue.c static void lockres_or_flags(struct ocfs2_lock_res *lockres, unsigned long or) or 904 fs/ocfs2/dlmglue.c lockres_set_flags(lockres, lockres->l_flags | or); or 134 include/asm-generic/atomic.h ATOMIC_FETCH_OP(or, |) or 146 include/asm-generic/atomic.h ATOMIC_OP(or, |) or 41 include/asm-generic/atomic64.h ATOMIC64_OPS(or) or 269 include/scsi/scsi_transport_fc.h is loop or the or 163 include/uapi/drm/msm_drm.h __u32 or; /* in, value OR'd with result */ or 125 lib/atomic64.c ATOMIC64_OPS(or, |=) or 118 lib/atomic64_test.c TEST(, or, |=, v1); or 170 lib/atomic64_test.c TEST(64, or, |=, v1); or 89 net/can/gw.c struct canfd_frame or; or 95 net/can/gw.c u8 or; or 161 net/can/gw.c MODFUNC(mod_or_id, cf->can_id |= mod->modframe.or.can_id) or 162 net/can/gw.c MODFUNC(mod_or_len, cf->len |= mod->modframe.or.len) or 163 net/can/gw.c MODFUNC(mod_or_flags, cf->flags |= mod->modframe.or.flags) or 164 net/can/gw.c MODFUNC(mod_or_data, *(u64 *)cf->data |= *(u64 *)mod->modframe.or.data) or 187 net/can/gw.c *(u64 *)(cf->data + i) |= *(u64 *)(mod->modframe.or.data + i); or 595 net/can/gw.c if (gwj->mod.modtype.or) { or 596 net/can/gw.c memcpy(&mb.cf, &gwj->mod.modframe.or, sizeof(mb.cf)); or 597 net/can/gw.c mb.modtype = gwj->mod.modtype.or; or 625 net/can/gw.c if (gwj->mod.modtype.or) { or 626 net/can/gw.c memcpy(&mb.cf, &gwj->mod.modframe.or, sizeof(mb.cf)); or 627 net/can/gw.c mb.modtype = gwj->mod.modtype.or; or 781 net/can/gw.c canfdframecpy(&mod->modframe.or, &mb.cf); or 782 net/can/gw.c mod->modtype.or = mb.modtype; or 856 net/can/gw.c canframecpy(&mod->modframe.or, &mb.cf); or 857 net/can/gw.c mod->modtype.or = mb.modtype; or 109 tools/bpf/bpf_exp.y | or or 406 tools/bpf/bpf_exp.y or or 166 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_VERY_LOW or 31,31,31 # very low priority or 167 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_LOW or 1,1,1 or 168 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority or 169 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_MEDIUM or 2,2,2 or 170 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority or 171 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_HIGH or 3,3,3 or 172 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define HMT_EXTRA_HIGH or 7,7,7 # power7 only