optc 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c static void optc1_disable_stereo(struct timing_generator *optc) optc 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc->funcs->program_global_sync(optc, optc 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc->funcs->set_vtg_params(optc, dc_crtc_timing); optc 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_set_vtg_params(struct timing_generator *optc, optc 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) optc 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 351 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c static void optc1_unblank_crtc(struct timing_generator *optc) optc 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_clear_optc_underflow(optc); optc 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c static void optc1_blank_crtc(struct timing_generator *optc) optc 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_set_blank_data_double_buffer(optc, false); optc 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_set_blank(struct timing_generator *optc, optc 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_blank_crtc(optc); optc 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_unblank_crtc(optc); optc 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_is_blanked(struct timing_generator *optc) optc 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) optc 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 442 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c static bool optc1_enable_crtc(struct timing_generator *optc) optc 448 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OPTC_SRC_SEL, optc->inst); optc 469 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_disable_crtc(struct timing_generator *optc) optc 471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 496 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 574 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t optc1_get_vblank_counter(struct timing_generator *optc) optc 576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 585 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_lock(struct timing_generator *optc) optc 587 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); optc 602 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { optc 610 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_unlock(struct timing_generator *optc) optc 612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 618 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_get_position(struct timing_generator *optc, optc 621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 631 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_is_counter_moving(struct timing_generator *optc) optc 635 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc->funcs->get_position(optc, &position1); optc 636 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc->funcs->get_position(optc, &position2); optc 646 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc) optc 648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 660 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_disable_reset_trigger(struct timing_generator *optc) optc 662 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) optc 675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 708 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 712 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 752 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_wait_for_state(struct timing_generator *optc, optc 755 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 776 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 786 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 789 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 804 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_setup_manual_trigger(struct timing_generator *optc) optc 806 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 809 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c MANUAL_FLOW_CONTROL_SEL, optc->inst); optc 813 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, optc 822 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_program_manual_trigger(struct timing_generator *optc) optc 824 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 844 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 879 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc->funcs->setup_manual_trigger(optc); optc 897 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 904 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct timing_generator *optc, optc 1162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_get_position(optc, &position); optc 1175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c static void optc1_enable_stereo(struct timing_generator *optc, optc 1178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_program_stereo(struct timing_generator *optc, optc 1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_enable_stereo(optc, timing, flags); optc 1213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_disable_stereo(optc); optc 1217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_is_stereo_left_eye(struct timing_generator *optc) optc 1221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_read_otg_state(struct optc *optc1, optc 1341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_get_otg_active_size(struct timing_generator *optc, optc 1350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_clear_optc_underflow(struct timing_generator *optc) optc 1374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_tg_init(struct timing_generator *optc) optc 1381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_set_blank_data_double_buffer(optc, true); optc 1382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_clear_optc_underflow(optc); optc 1385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_is_tg_enabled(struct timing_generator *optc) optc 1387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) optc 1398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_configure_crc(struct timing_generator *optc, optc 1411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (!optc1_is_tg_enabled(optc)) optc 1452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_get_crc(struct timing_generator *optc, optc 1456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 1520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void dcn10_timing_generator_init(struct optc *optc1) optc 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h container_of(tg, struct optc, base) optc 524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void dcn10_timing_generator_init(struct optc *optc); optc 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_read_otg_state(struct optc *optc1, optc 555 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 559 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 580 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 586 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_disable_crtc(struct timing_generator *optc); optc 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_is_counter_moving(struct timing_generator *optc); optc 590 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_get_position(struct timing_generator *optc, optc 593 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t optc1_get_vblank_counter(struct timing_generator *optc); optc 596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 603 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 606 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_wait_for_state(struct timing_generator *optc, optc 609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_set_blank(struct timing_generator *optc, optc 612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_is_blanked(struct timing_generator *optc); optc 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 619 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc); optc 621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); optc 623 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_disable_reset_trigger(struct timing_generator *optc); optc 625 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_lock(struct timing_generator *optc); optc 627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_unlock(struct timing_generator *optc); optc 629 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); optc 632 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 636 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 639 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_program_stereo(struct timing_generator *optc, optc 642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_is_stereo_left_eye(struct timing_generator *optc); optc 644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_clear_optc_underflow(struct timing_generator *optc); optc 646 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_tg_init(struct timing_generator *optc); optc 648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_is_tg_enabled(struct timing_generator *optc); optc 650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); optc 652 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); optc 654 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_get_otg_active_size(struct timing_generator *optc, optc 659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator *optc, optc 663 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_configure_crc(struct timing_generator *optc, optc 666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_get_crc(struct timing_generator *optc, optc 671 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_set_vtg_params(struct timing_generator *optc, optc 720 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct optc *tgn10 = optc 721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kzalloc(sizeof(struct optc), GFP_KERNEL); optc 1363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct timing_generator *optc; optc 1372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst]; optc 1373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); optc 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c bool optc2_enable_crtc(struct timing_generator *optc) optc 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OPTC_SEG0_SRC_SEL, optc->inst); optc 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable) optc 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_gsl(struct timing_generator *optc, optc 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc, optc 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_gsl_window(struct timing_generator *optc, optc 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_vupdate_keepout(struct timing_generator *optc, optc 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct timing_generator *optc, optc 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc, optc 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_dsc_config(struct timing_generator *optc, optc 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_odm_bypass(struct timing_generator *optc, optc 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OPTC_SEG0_SRC_SEL, optc->inst, optc 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, optc 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_get_optc_source(struct timing_generator *optc, optc 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_dwb_source(struct timing_generator *optc, optc 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 311 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OPTC_DWB0_SOURCE_SELECT, optc->inst); optc 314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OPTC_DWB1_SOURCE_SELECT, optc->inst); optc 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_triplebuffer_lock(struct timing_generator *optc) optc 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); optc 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) optc 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_triplebuffer_unlock(struct timing_generator *optc) optc 338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_lock_doublebuffer_enable(struct timing_generator *optc) optc 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_lock_doublebuffer_disable(struct timing_generator *optc) optc 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_setup_manual_trigger(struct timing_generator *optc) optc 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 394 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c MANUAL_FLOW_CONTROL_SEL, optc->inst); optc 398 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, optc 407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_program_manual_trigger(struct timing_generator *optc) optc 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void dcn20_timing_generator_init(struct optc *optc1) optc 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void dcn20_timing_generator_init(struct optc *optc); optc 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h bool optc2_enable_crtc(struct timing_generator *optc); optc 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_set_gsl(struct timing_generator *optc, optc 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_set_gsl_source_select(struct timing_generator *optc, optc 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_set_dsc_config(struct timing_generator *optc, optc 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_set_odm_bypass(struct timing_generator *optc, optc 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, optc 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_get_optc_source(struct timing_generator *optc, optc 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_triplebuffer_lock(struct timing_generator *optc); optc 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_triplebuffer_unlock(struct timing_generator *optc); optc 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_lock_doublebuffer_disable(struct timing_generator *optc); optc 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_lock_doublebuffer_enable(struct timing_generator *optc); optc 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_program_manual_trigger(struct timing_generator *optc); optc 1122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct optc *tgn10 = optc 1123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kzalloc(sizeof(struct optc), GFP_KERNEL); optc 1212 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct optc *tgn10 = optc 1213 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kzalloc(sizeof(struct optc), GFP_KERNEL); optc 149 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h struct timing_generator *optc, optc 153 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h struct timing_generator *optc, optc 156 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h struct timing_generator *optc, optc 172 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h bool (*get_otg_active_size)(struct timing_generator *optc, optc 239 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_dwb_source)(struct timing_generator *optc, optc 242 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*get_optc_source)(struct timing_generator *optc, optc 262 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*program_manual_trigger)(struct timing_generator *optc); optc 263 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*setup_manual_trigger)(struct timing_generator *optc); optc 265 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_vtg_params)(struct timing_generator *optc, optc 270 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_dsc_config)(struct timing_generator *optc, optc 275 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); optc 276 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, optc 278 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); optc 279 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_gsl_source_select)(struct timing_generator *optc,