omap_hwmod_write  343 arch/arm/mach-omap2/display.c 	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
omap_hwmod_write  348 arch/arm/mach-omap2/display.c 	omap_hwmod_write(v, oh, DISPC_CONTROL);
omap_hwmod_write  354 arch/arm/mach-omap2/display.c 		omap_hwmod_write(v, oh, DISPC_CONTROL2);
omap_hwmod_write  361 arch/arm/mach-omap2/display.c 		omap_hwmod_write(v, oh, DISPC_CONTROL3);
omap_hwmod_write  395 arch/arm/mach-omap2/display.c 		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
omap_hwmod_write  396 arch/arm/mach-omap2/display.c 		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
omap_hwmod_write  403 arch/arm/mach-omap2/display.c 	omap_hwmod_write(0x0, oh, DSS_CONTROL);
omap_hwmod_write   48 arch/arm/mach-omap2/hdq1w.c 	omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
omap_hwmod_write   50 arch/arm/mach-omap2/i2c.c 	omap_hwmod_write(v, oh, i2c_con);
omap_hwmod_write   58 arch/arm/mach-omap2/i2c.c 	omap_hwmod_write(v, oh, i2c_con);
omap_hwmod_write   56 arch/arm/mach-omap2/msdi.c 	omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
omap_hwmod_write   72 arch/arm/mach-omap2/msdi.c 	omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
omap_hwmod_write  316 arch/arm/mach-omap2/omap_hwmod.c 	omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
omap_hwmod_write  637 arch/arm/mach-omap2/omap_hwmod.h void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
omap_hwmod_write   99 arch/arm/mach-omap2/omap_hwmod_reset.c 	omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG);
omap_hwmod_write  100 arch/arm/mach-omap2/omap_hwmod_reset.c 	omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG);
omap_hwmod_write  119 arch/arm/mach-omap2/omap_hwmod_reset.c 	omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG);
omap_hwmod_write  120 arch/arm/mach-omap2/omap_hwmod_reset.c 	omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG);