omap3_dpll4_set_rate_and_parent 299 drivers/clk/ti/clock.h int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, omap3_dpll4_set_rate_and_parent 142 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,