omap2_prm_write_mod_reg  195 arch/arm/mach-omap2/pm24xx.c 	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
omap2_prm_write_mod_reg  226 arch/arm/mach-omap2/pm24xx.c 	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
omap2_prm_write_mod_reg  230 arch/arm/mach-omap2/pm24xx.c 	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
omap2_prm_write_mod_reg  232 arch/arm/mach-omap2/pm24xx.c 	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
omap2_prm_write_mod_reg  240 arch/arm/mach-omap2/pm24xx.c 	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
omap2_prm_write_mod_reg  129 arch/arm/mach-omap2/prm2xxx.c 	omap2_prm_write_mod_reg(wkst, module, regs);
omap2_prm_write_mod_reg   72 arch/arm/mach-omap2/prm2xxx_3xxx.h 	omap2_prm_write_mod_reg(v, module, idx);
omap2_prm_write_mod_reg  111 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(vp->tranxdone_status,
omap2_prm_write_mod_reg  122 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
omap2_prm_write_mod_reg  192 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
omap2_prm_write_mod_reg  210 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
omap2_prm_write_mod_reg  253 arch/arm/mach-omap2/prm3xxx.c 			omap2_prm_write_mod_reg(wkst, module, wkst_off);
omap2_prm_write_mod_reg  273 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(
omap2_prm_write_mod_reg  277 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
omap2_prm_write_mod_reg  303 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
omap2_prm_write_mod_reg  307 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
omap2_prm_write_mod_reg  313 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
omap2_prm_write_mod_reg  325 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(en_uart4_mask |
omap2_prm_write_mod_reg  338 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(grpsel_uart4_mask |
omap2_prm_write_mod_reg  352 arch/arm/mach-omap2/prm3xxx.c 		omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
omap2_prm_write_mod_reg  353 arch/arm/mach-omap2/prm3xxx.c 		omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
omap2_prm_write_mod_reg  354 arch/arm/mach-omap2/prm3xxx.c 		omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
omap2_prm_write_mod_reg  355 arch/arm/mach-omap2/prm3xxx.c 		omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
omap2_prm_write_mod_reg  360 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg  361 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg  362 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg  363 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg  364 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg  365 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg  366 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
omap2_prm_write_mod_reg  370 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
omap2_prm_write_mod_reg  483 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
omap2_prm_write_mod_reg  493 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
omap2_prm_write_mod_reg  499 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
omap2_prm_write_mod_reg  617 arch/arm/mach-omap2/prm3xxx.c 	omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);