nwl_bridge_writel 316 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); nwl_bridge_writel 355 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, 1 << bit, status_reg); nwl_bridge_writel 395 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); nwl_bridge_writel 411 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); nwl_bridge_writel 617 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | nwl_bridge_writel 621 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | nwl_bridge_writel 626 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); nwl_bridge_writel 627 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); nwl_bridge_writel 633 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); nwl_bridge_writel 635 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & nwl_bridge_writel 638 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); nwl_bridge_writel 644 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); nwl_bridge_writel 646 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & nwl_bridge_writel 649 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); nwl_bridge_writel 672 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), nwl_bridge_writel 674 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), nwl_bridge_writel 678 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, nwl_bridge_writel 682 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | nwl_bridge_writel 686 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); nwl_bridge_writel 689 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, nwl_bridge_writel 703 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | nwl_bridge_writel 706 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | nwl_bridge_writel 710 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), nwl_bridge_writel 712 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), nwl_bridge_writel 747 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); nwl_bridge_writel 750 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & nwl_bridge_writel 754 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); nwl_bridge_writel 758 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); nwl_bridge_writel 761 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & nwl_bridge_writel 765 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); nwl_bridge_writel 768 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |