nvkm_rd32 267 drivers/gpu/drm/nouveau/include/nvkm/core/device.h u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \ nvkm_rd32 96 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h return nvkm_rd32(falcon->owner->device, falcon->addr + addr); nvkm_rd32 71 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h if ((nvkm_rd32(d, (addr)) & (mask)) == (data)) \ nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 stat = nvkm_rd32(device, 0x104f14 + base); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 mask = nvkm_rd32(device, 0x104904 + base); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 stat = nvkm_rd32(device, 0x104418 + base); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 mask = nvkm_rd32(device, 0x10440c + base); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; nvkm_rd32 48 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; nvkm_rd32 49 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 data = nvkm_rd32(device, 0x104044 + base); nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c u32 stat = nvkm_rd32(device, 0x102130); nvkm_rd32 87 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c u32 mthd = nvkm_rd32(device, 0x102190); nvkm_rd32 88 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c u32 data = nvkm_rd32(device, 0x102194); nvkm_rd32 89 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff; nvkm_rd32 253 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c *data = nvkm_rd32(udev->device, addr); nvkm_rd32 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 next = nvkm_rd32(device, list->data[i].addr + base + 0); nvkm_rd32 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 prev = nvkm_rd32(device, list->data[i].addr + base + c); nvkm_rd32 182 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c *data = nvkm_rd32(device, base + addr); nvkm_rd32 179 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c if (!(nvkm_rd32(device, 0x610490) & 0x001e0000)) nvkm_rd32 183 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c nvkm_rd32(device, 0x610490)); nvkm_rd32 203 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c if (!(nvkm_rd32(device, 0x610490) & 0x80000000)) nvkm_rd32 207 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c nvkm_rd32(device, 0x610490)); nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c if (!(nvkm_rd32(device, 0x610490) & 0x80000000)) nvkm_rd32 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c nvkm_rd32(device, 0x610490)); nvkm_rd32 140 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c u32 stat = nvkm_rd32(device, 0x610630); nvkm_rd32 176 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c if (!(nvkm_rd32(device, 0x610200) & 0x001e0000)) nvkm_rd32 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c nvkm_rd32(device, 0x610200)); nvkm_rd32 191 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000) nvkm_rd32 193 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000) nvkm_rd32 206 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c if (!(nvkm_rd32(device, 0x610200) & 0x80000000)) nvkm_rd32 210 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c nvkm_rd32(device, 0x610200)); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c u32 stat = nvkm_rd32(device, 0x610664 + soff); nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c u32 ctrl = nvkm_rd32(device, 0x640180 + coff); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c *pmask = (nvkm_rd32(device, 0x612004) & 0x000000f0) >> 4; nvkm_rd32 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000)) nvkm_rd32 88 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c u32 ctrl = nvkm_rd32(device, 0x610b58 + coff); nvkm_rd32 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c *pmask = (nvkm_rd32(device, 0x610184) & 0x00700000) >> 20; nvkm_rd32 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000)) nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000)) nvkm_rd32 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000)) nvkm_rd32 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c u32 stat = nvkm_rd32(device, 0x610664 + soff); nvkm_rd32 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x001e0000)) nvkm_rd32 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); nvkm_rd32 117 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x80000000)) nvkm_rd32 121 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); nvkm_rd32 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 stat = nvkm_rd32(device, 0x6101f0 + (chid * 12)); nvkm_rd32 97 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12)); nvkm_rd32 98 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 code = nvkm_rd32(device, 0x6101f8 + (chid * 12)); nvkm_rd32 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 intr = nvkm_rd32(device, 0x610088); nvkm_rd32 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 stat = nvkm_rd32(device, 0x61008c); nvkm_rd32 140 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 stat = nvkm_rd32(device, 0x61009c); nvkm_rd32 148 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 stat = nvkm_rd32(device, 0x6100ac); nvkm_rd32 168 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 stat = nvkm_rd32(device, 0x6100bc + hoff); nvkm_rd32 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_rd32(device, 0x6100c0 + hoff); nvkm_rd32 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c tmp = nvkm_rd32(device, 0x616104 + hoff); nvkm_rd32 203 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c tmp = nvkm_rd32(device, 0x616108 + hoff); nvkm_rd32 205 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c tmp = nvkm_rd32(device, 0x61610c + hoff); nvkm_rd32 211 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); nvkm_rd32 217 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); nvkm_rd32 222 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (nvkm_rd32(device, 0x6100ac) & 0x00000100) { nvkm_rd32 226 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002)) nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12)); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12)); nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12)); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c *pmask = nvkm_rd32(device, 0x610064); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20; nvkm_rd32 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 stat = nvkm_rd32(device, 0x6107a8); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4)); nvkm_rd32 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); nvkm_rd32 104 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); nvkm_rd32 105 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); nvkm_rd32 132 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 stat = nvkm_rd32(device, 0x611c30); nvkm_rd32 148 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c unsigned long wndws = nvkm_rd32(device, 0x611858); nvkm_rd32 149 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c unsigned long other = nvkm_rd32(device, 0x61185c); nvkm_rd32 174 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 stat = nvkm_rd32(device, 0x611854); nvkm_rd32 203 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c unsigned long stat = nvkm_rd32(device, 0x611850); nvkm_rd32 223 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c unsigned long stat = nvkm_rd32(device, 0x61184c); nvkm_rd32 243 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04)); nvkm_rd32 268 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 stat = nvkm_rd32(device, 0x611ec0); nvkm_rd32 319 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { nvkm_rd32 322 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) nvkm_rd32 329 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c tmp = nvkm_rd32(device, 0x610068); nvkm_rd32 334 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); nvkm_rd32 344 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); nvkm_rd32 349 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j); nvkm_rd32 358 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j); nvkm_rd32 365 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); nvkm_rd32 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c data = nvkm_rd32(device, 0x640414 + hoff); nvkm_rd32 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c data = nvkm_rd32(device, 0x640418 + hoff); nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c data = nvkm_rd32(device, 0x64041c + hoff); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c data = nvkm_rd32(device, 0x640420 + hoff); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c state->hz = nvkm_rd32(device, 0x640450 + hoff); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c data = nvkm_rd32(device, 0x640404 + hoff); nvkm_rd32 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c *pmask = nvkm_rd32(device, 0x612004) & 0x0000000f; nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c return nvkm_rd32(device, 0x022448); nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c *hline = nvkm_rd32(device, 0x616334 + hoff) & 0x0000ffff; nvkm_rd32 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c data = nvkm_rd32(device, 0x682064 + hoff); nvkm_rd32 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c data = nvkm_rd32(device, 0x682068 + hoff); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c data = nvkm_rd32(device, 0x68206c + hoff); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c data = nvkm_rd32(device, 0x682070 + hoff); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c state->hz = nvkm_rd32(device, 0x68200c + hoff); nvkm_rd32 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c data = nvkm_rd32(device, 0x682004 + hoff); nvkm_rd32 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c if (!(nvkm_rd32(device, 0x610060) & (0x00000001 << id))) nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c *pmask = nvkm_rd32(device, 0x610060) & 0x000000ff; nvkm_rd32 104 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c return nvkm_rd32(device, 0x610074) & 0x0000000f; nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c u32 data = nvkm_rd32(device, 0x600868 + (head->id * 0x2000)); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c state->vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0x0000ffff; nvkm_rd32 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c state->vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0x0000ffff; nvkm_rd32 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c state->hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0x0000ffff; nvkm_rd32 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c state->htotal = nvkm_rd32(device, 0x680824 + hoff) & 0x0000ffff; nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c *vline = nvkm_rd32(device, 0x616340 + hoff) & 0x0000ffff; nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c *hline = nvkm_rd32(device, 0x616344 + hoff) & 0x0000ffff; nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c data = nvkm_rd32(device, 0x610ae8 + hoff); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c data = nvkm_rd32(device, 0x610af0 + hoff); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c data = nvkm_rd32(device, 0x610af8 + hoff); nvkm_rd32 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c data = nvkm_rd32(device, 0x610b00 + hoff); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c state->hz = (nvkm_rd32(device, 0x610ad0 + hoff) & 0x003fffff) * 1000; nvkm_rd32 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c u32 crtc0 = nvkm_rd32(device, 0x600100); nvkm_rd32 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c u32 crtc1 = nvkm_rd32(device, 0x602100); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c pvideo = nvkm_rd32(device, 0x8100); nvkm_rd32 551 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c u32 super = nvkm_rd32(device, 0x610030); nvkm_rd32 618 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08)); nvkm_rd32 619 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08)); nvkm_rd32 651 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c u32 intr0 = nvkm_rd32(device, 0x610020); nvkm_rd32 652 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c u32 intr1 = nvkm_rd32(device, 0x610024); nvkm_rd32 704 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x614004); nvkm_rd32 709 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x616100 + (head->id * 0x800)); nvkm_rd32 711 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x616104 + (head->id * 0x800)); nvkm_rd32 713 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x616108 + (head->id * 0x800)); nvkm_rd32 715 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x61610c + (head->id * 0x800)); nvkm_rd32 721 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); nvkm_rd32 727 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); nvkm_rd32 733 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800)); nvkm_rd32 738 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (nvkm_rd32(device, 0x610024) & 0x00000100) { nvkm_rd32 742 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002)) nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000)) nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); nvkm_rd32 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10)); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); nvkm_rd32 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); nvkm_rd32 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c u32 tmp = nvkm_rd32(device, 0x610200 + (ctrl * 0x10)); nvkm_rd32 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c if (!(nvkm_rd32(device, 0x61e004 + poff) & 0x80000000)) nvkm_rd32 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c u32 ctrl = nvkm_rd32(device, 0x610b80 + coff); nvkm_rd32 137 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c *pmask = (nvkm_rd32(device, 0x610184) & 0x70000000) >> 28; nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c data[2] = nvkm_rd32(device, 0x61c130 + loff); nvkm_rd32 97 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000)) nvkm_rd32 128 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) { nvkm_rd32 151 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c clksor = nvkm_rd32(device, 0x614300 + nv50_ior_base(ior)); nvkm_rd32 178 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c sorpwr = nvkm_rd32(device, 0x61c004 + soff); nvkm_rd32 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c u32 seqctl = nvkm_rd32(device, 0x61c030 + soff); nvkm_rd32 187 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) nvkm_rd32 192 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) nvkm_rd32 229 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (nvkm_rd32(device, 0x61c004 + soff) & 0x00000001) { nvkm_rd32 230 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c u32 seqctl = nvkm_rd32(device, 0x61c030 + soff); nvkm_rd32 241 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c u32 ctrl = nvkm_rd32(device, 0x610794 + coff); nvkm_rd32 289 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c *pmask = (nvkm_rd32(device, 0x610184) & 0x0f000000) >> 24; nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000)) nvkm_rd32 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); nvkm_rd32 79 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); nvkm_rd32 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c data[2] = nvkm_rd32(device, 0x61c130 + loff); nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); nvkm_rd32 140 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u32 ctrl = nvkm_rd32(device, 0x640200 + coff); nvkm_rd32 193 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c *pmask = (nvkm_rd32(device, 0x612004) & 0x0000ff00) >> 8; nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); nvkm_rd32 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c data[2] = nvkm_rd32(device, 0x61c130 + loff); nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); nvkm_rd32 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c u32 data = nvkm_rd32(device, 0x612308 + (m * 0x80)); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c if (!(nvkm_rd32(device, 0x61c1e0 + soff) & 0x80000000)) nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c if (!(nvkm_rd32(device, 0x616560 + hoff) & 0x80000000)) nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c u32 ctrl = nvkm_rd32(device, 0x680300 + coff); nvkm_rd32 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c *pmask = (nvkm_rd32(device, 0x610060) & 0x0000ff00) >> 8; nvkm_rd32 120 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c return (nvkm_rd32(device, 0x610074) & 0x00000f00) >> 8; nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000)) nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) nvkm_rd32 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c u32 ctrl = nvkm_rd32(device, 0x610b70 + coff); nvkm_rd32 104 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c *pmask = (nvkm_rd32(device, 0x610184) & 0x03000000) >> 24; nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) nvkm_rd32 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j); nvkm_rd32 79 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j); nvkm_rd32 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); nvkm_rd32 137 drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c if (!(nvkm_rd32(device, 0x001084) & 0x10000000)) nvkm_rd32 166 drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c u32 tied = nvkm_rd32(device, 0x001084) & 0x10000000; nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u32 dest = nvkm_rd32(device, base + 0x01c); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff; nvkm_rd32 143 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c caps = nvkm_rd32(device, base + 0x12c); nvkm_rd32 148 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c caps = nvkm_rd32(device, base + 0x108); nvkm_rd32 174 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (nvkm_rd32(device, base + 0x008) & 0x00000010) nvkm_rd32 179 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!(nvkm_rd32(device, base + 0x180) & 0x80000000)) nvkm_rd32 109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) nvkm_rd32 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) nvkm_rd32 91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask; nvkm_rd32 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); nvkm_rd32 107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c !(nvkm_rd32(device, 0x00227c) & 0x00100000), nvkm_rd32 327 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); nvkm_rd32 355 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x00254c); nvkm_rd32 376 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); nvkm_rd32 377 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); nvkm_rd32 378 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); nvkm_rd32 379 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); nvkm_rd32 409 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); nvkm_rd32 410 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); nvkm_rd32 411 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); nvkm_rd32 412 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; nvkm_rd32 447 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x002a00); nvkm_rd32 466 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); nvkm_rd32 467 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 inte = nvkm_rd32(device, 0x002628); nvkm_rd32 490 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x0025a4); nvkm_rd32 504 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x002140); nvkm_rd32 505 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 stat = nvkm_rd32(device, 0x002100) & mask; nvkm_rd32 508 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x00252c); nvkm_rd32 521 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x00256c); nvkm_rd32 528 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x00258c); nvkm_rd32 535 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x00259c); nvkm_rd32 546 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x0025a0); nvkm_rd32 584 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x002204)); nvkm_rd32 58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); nvkm_rd32 172 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (!(nvkm_rd32(device, 0x002284 + (runl * 0x08)) & 0x00100000)) nvkm_rd32 265 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c return hweight32(nvkm_rd32(device, 0x000204)); nvkm_rd32 361 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08)); nvkm_rd32 564 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 intr = nvkm_rd32(device, 0x00252c); nvkm_rd32 614 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 intr = nvkm_rd32(device, 0x00254c); nvkm_rd32 635 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x00256c); nvkm_rd32 645 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x00259c); nvkm_rd32 688 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000)); nvkm_rd32 689 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask; nvkm_rd32 690 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); nvkm_rd32 691 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); nvkm_rd32 692 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; nvkm_rd32 737 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000)); nvkm_rd32 738 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask; nvkm_rd32 739 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; nvkm_rd32 746 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_rd32(device, 0x040150 + (unit * 0x2000)), nvkm_rd32 747 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_rd32(device, 0x040154 + (unit * 0x2000))); nvkm_rd32 757 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x002a00); nvkm_rd32 778 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x002140); nvkm_rd32 779 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x002100) & mask; nvkm_rd32 824 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x00259c); nvkm_rd32 835 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x0025a0); nvkm_rd32 921 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); nvkm_rd32 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); nvkm_rd32 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); nvkm_rd32 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c return nvkm_rd32(device, 0x002004) & 0x000000ff; nvkm_rd32 59 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); nvkm_rd32 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); nvkm_rd32 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c if (nvkm_rd32(device, 0x002634) == chan->base.chid) nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c if (!(nvkm_rd32(device, 0x002634) & 0x00100000)) nvkm_rd32 188 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */ nvkm_rd32 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & nvkm_rd32 114 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 engine = nvkm_rd32(device, 0x003280); nvkm_rd32 122 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c data = nvkm_rd32(device, 0x003258) & 0x0000ffff; nvkm_rd32 143 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 pull0 = nvkm_rd32(device, 0x003250); nvkm_rd32 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); nvkm_rd32 156 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); nvkm_rd32 158 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); nvkm_rd32 159 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); nvkm_rd32 176 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); nvkm_rd32 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1); nvkm_rd32 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); nvkm_rd32 192 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 dma_get = nvkm_rd32(device, 0x003244); nvkm_rd32 193 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 dma_put = nvkm_rd32(device, 0x003240); nvkm_rd32 194 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 push = nvkm_rd32(device, 0x003220); nvkm_rd32 195 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 state = nvkm_rd32(device, 0x003228); nvkm_rd32 203 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 ho_get = nvkm_rd32(device, 0x003328); nvkm_rd32 204 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 ho_put = nvkm_rd32(device, 0x003320); nvkm_rd32 205 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 ib_get = nvkm_rd32(device, 0x003334); nvkm_rd32 206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 ib_put = nvkm_rd32(device, 0x003330); nvkm_rd32 245 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); nvkm_rd32 246 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; nvkm_rd32 249 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; nvkm_rd32 252 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1); nvkm_rd32 253 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); nvkm_rd32 269 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c if (nvkm_rd32(device, 0x002600 + (i * 4)) & 0x80000000) nvkm_rd32 1098 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const u8 gpcmax = nvkm_rd32(device, 0x022430); nvkm_rd32 1099 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const u8 tpcmax = nvkm_rd32(device, 0x022434) * gpcmax; nvkm_rd32 1164 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c u32 fbps = nvkm_rd32(device, 0x121c74); nvkm_rd32 1455 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (!(nvkm_rd32(device, 0x404170) & 0x00000010)) nvkm_rd32 1467 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_rd32(device, 0x409614); nvkm_rd32 1541 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (nvkm_rd32(device, 0x409800) & 0x80000000) nvkm_rd32 1554 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (!(nvkm_rd32(device, 0x409b00) & 0x80000000)) nvkm_rd32 867 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c u32 data0 = nvkm_rd32(device, 0x17e91c); nvkm_rd32 868 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c u32 data1 = nvkm_rd32(device, 0x17e920); nvkm_rd32 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); nvkm_rd32 183 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_rd32(device, 0x40988c); nvkm_rd32 185 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_rd32(device, 0x41a88c); nvkm_rd32 187 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_rd32(device, 0x408a14); nvkm_rd32 302 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c u32 units = nvkm_rd32(device, 0x1540); nvkm_rd32 1195 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c u32 units = nvkm_rd32(device, 0x1540); nvkm_rd32 3278 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c u32 units = nvkm_rd32(device, 0x1540); nvkm_rd32 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { nvkm_rd32 139 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { nvkm_rd32 144 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { nvkm_rd32 154 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c tmp = nvkm_rd32(device, 0x400700); nvkm_rd32 159 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_rd32(device, 0x400380)); nvkm_rd32 161 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_rd32(device, 0x400384)); nvkm_rd32 163 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_rd32(device, 0x400388)); nvkm_rd32 169 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) nvkm_rd32 721 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return nvkm_rd32(gr->engine.subdev.device, 0x409b00); nvkm_rd32 734 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x409804); nvkm_rd32 783 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x409800); nvkm_rd32 803 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (nvkm_rd32(device, 0x409800) == 0x00000001) nvkm_rd32 820 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (nvkm_rd32(device, 0x409800) == 0x00000001) nvkm_rd32 836 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if ((*psize = nvkm_rd32(device, 0x409800))) nvkm_rd32 874 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if ((*psize = nvkm_rd32(device, 0x409800))) nvkm_rd32 890 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if ((*psize = nvkm_rd32(device, 0x409800))) nvkm_rd32 906 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if ((*psize = nvkm_rd32(device, 0x409800))) nvkm_rd32 928 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); nvkm_rd32 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); nvkm_rd32 943 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; nvkm_rd32 1003 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, 0x400700); nvkm_rd32 1005 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; nvkm_rd32 1006 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; nvkm_rd32 1007 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; nvkm_rd32 1064 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) nvkm_rd32 1181 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; nvkm_rd32 1182 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); nvkm_rd32 1183 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); nvkm_rd32 1184 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); nvkm_rd32 1239 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); nvkm_rd32 1240 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); nvkm_rd32 1260 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); nvkm_rd32 1263 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); nvkm_rd32 1275 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); nvkm_rd32 1282 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); nvkm_rd32 1289 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); nvkm_rd32 1305 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); nvkm_rd32 1314 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); nvkm_rd32 1321 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); nvkm_rd32 1328 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); nvkm_rd32 1354 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, 0x400108); nvkm_rd32 1358 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x404000); nvkm_rd32 1369 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x404600); nvkm_rd32 1381 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x408030); nvkm_rd32 1392 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x405840); nvkm_rd32 1401 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x40601c); nvkm_rd32 1413 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x404490); nvkm_rd32 1414 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 pc = nvkm_rd32(device, 0x404494); nvkm_rd32 1415 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 op = nvkm_rd32(device, 0x40449c); nvkm_rd32 1430 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; nvkm_rd32 1442 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x400118); nvkm_rd32 1457 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); nvkm_rd32 1458 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); nvkm_rd32 1480 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x400)); nvkm_rd32 1482 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x800), nvkm_rd32 1483 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x804), nvkm_rd32 1484 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x808), nvkm_rd32 1485 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x80c)); nvkm_rd32 1487 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x810), nvkm_rd32 1488 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x814), nvkm_rd32 1489 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x818), nvkm_rd32 1490 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x81c)); nvkm_rd32 1497 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; nvkm_rd32 1510 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x409c18); nvkm_rd32 1513 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 code = nvkm_rd32(device, 0x409814); nvkm_rd32 1515 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 class = nvkm_rd32(device, 0x409808); nvkm_rd32 1516 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 addr = nvkm_rd32(device, 0x40980c); nvkm_rd32 1519 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 data = nvkm_rd32(device, 0x409810); nvkm_rd32 1553 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; nvkm_rd32 1554 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, 0x400100); nvkm_rd32 1555 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 addr = nvkm_rd32(device, 0x400704); nvkm_rd32 1558 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 data = nvkm_rd32(device, 0x400708); nvkm_rd32 1559 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 code = nvkm_rd32(device, 0x400110); nvkm_rd32 1571 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c class = nvkm_rd32(device, 0x404200 + (subc * 4)); nvkm_rd32 1657 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c star = nvkm_rd32(device, falcon + 0x01c4); nvkm_rd32 1658 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c temp = nvkm_rd32(device, falcon + 0x01c4); nvkm_rd32 1728 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (nvkm_rd32(device, 0x409800) & 0x00000001) nvkm_rd32 1814 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (nvkm_rd32(device, 0x409800) & 0x80000000) nvkm_rd32 1821 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->size = nvkm_rd32(device, 0x409804); nvkm_rd32 1959 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; nvkm_rd32 1961 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); nvkm_rd32 1967 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); nvkm_rd32 2013 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, 0x000200); nvkm_rd32 2016 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, 0x000200); nvkm_rd32 2261 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001); nvkm_rd32 2275 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); nvkm_rd32 409 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c const u32 fbp_count = nvkm_rd32(device, 0x120074); nvkm_rd32 193 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c if (!(nvkm_rd32(device, 0x40910c) & 0x00000006)) nvkm_rd32 201 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006)) nvkm_rd32 324 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c u32 save = nvkm_rd32(device, 0x619444); nvkm_rd32 38 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); nvkm_rd32 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c const u32 fbp_count = nvkm_rd32(device, 0x12006c); nvkm_rd32 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c if (nvkm_rd32(device, 0x100ce4) != 0xffffffff) nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c val = nvkm_rd32(device, 0x100c80); nvkm_rd32 50 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); nvkm_rd32 98 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f; nvkm_rd32 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); nvkm_rd32 447 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; nvkm_rd32 450 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c tmp = nvkm_rd32(device, 0x700000 + inst); nvkm_rd32 465 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c ctx1 = nvkm_rd32(device, 0x700000 + inst); nvkm_rd32 469 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c tmp = nvkm_rd32(device, 0x70000c + inst); nvkm_rd32 510 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u8 class = nvkm_rd32(device, 0x700000) & 0x000000ff; nvkm_rd32 561 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c return nvkm_rd32(device, 0x700000 + (inst << 4)); nvkm_rd32 1018 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (nvkm_rd32(device, 0x700000 + inst) & 0x000000ff) { nvkm_rd32 1076 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (nvkm_rd32(device, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { nvkm_rd32 1077 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24; nvkm_rd32 1106 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c chan->nv04[i] = nvkm_rd32(device, nv04_gr_ctx_regs[i]); nvkm_rd32 1129 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; nvkm_rd32 1221 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask)) nvkm_rd32 1225 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nvkm_rd32(device, NV04_PGRAPH_STATUS)); nvkm_rd32 1277 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); nvkm_rd32 1278 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); nvkm_rd32 1279 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); nvkm_rd32 1280 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); nvkm_rd32 1284 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); nvkm_rd32 1285 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff; nvkm_rd32 1286 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4; nvkm_rd32 419 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c state[__i] = nvkm_rd32(device, NV10_PGRAPH_PIPE_DATA); \ nvkm_rd32 454 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); nvkm_rd32 455 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); nvkm_rd32 551 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (nvkm_rd32(device, 0x400144) & 0x00010000) { nvkm_rd32 552 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c int chid = nvkm_rd32(device, 0x400148) >> 24; nvkm_rd32 589 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); nvkm_rd32 590 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); nvkm_rd32 827 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; nvkm_rd32 839 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c ctx_user = nvkm_rd32(device, NV10_PGRAPH_CTX_USER); nvkm_rd32 841 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c ctx_switch[i] = nvkm_rd32(device, NV10_PGRAPH_CTX_SWITCH(i)); nvkm_rd32 844 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c st2 = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2); nvkm_rd32 845 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c st2_dl = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DL); nvkm_rd32 846 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c st2_dh = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DH); nvkm_rd32 847 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c fifo_ptr = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR); nvkm_rd32 850 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c fifo[i] = nvkm_rd32(device, 0x4007a0 + 4 * i); nvkm_rd32 855 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(subchan, i))); nvkm_rd32 900 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; nvkm_rd32 917 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan->nv10[i] = nvkm_rd32(device, nv10_gr_ctx_regs[i]); nvkm_rd32 921 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan->nv17[i] = nvkm_rd32(device, nv17_gr_ctx_regs[i]); nvkm_rd32 947 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; nvkm_rd32 1027 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_rd32(device, NV10_PGRAPH_DEBUG_4)); nvkm_rd32 1028 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0)); nvkm_rd32 1086 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); nvkm_rd32 1087 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); nvkm_rd32 1088 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); nvkm_rd32 1089 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); nvkm_rd32 1093 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); nvkm_rd32 1094 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; nvkm_rd32 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c if (nvkm_rd32(device, 0x400144) & 0x00010000) nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c if (!nvkm_rd32(device, 0x400700)) nvkm_rd32 186 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); nvkm_rd32 187 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); nvkm_rd32 188 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); nvkm_rd32 189 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); nvkm_rd32 193 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); nvkm_rd32 194 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; nvkm_rd32 244 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c if (!nvkm_rd32(device, 0x400700)) nvkm_rd32 252 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c if (!nvkm_rd32(device, 0x400700)) nvkm_rd32 287 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324)); nvkm_rd32 289 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324)); nvkm_rd32 294 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00; nvkm_rd32 296 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100; nvkm_rd32 301 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_rd32 302 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); nvkm_rd32 304 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200)); nvkm_rd32 306 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204)); nvkm_rd32 153 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_rd32 154 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); nvkm_rd32 157 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); nvkm_rd32 159 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c return nvkm_rd32(gr->engine.subdev.device, 0x1540); nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c if (nvkm_rd32(device, 0x40032c) == inst) { nvkm_rd32 110 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c if (!(nvkm_rd32(device, 0x400300) & 0x00000001)) nvkm_rd32 113 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 insn = nvkm_rd32(device, 0x400308); nvkm_rd32 122 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c if (nvkm_rd32(device, 0x400330) == inst) nvkm_rd32 238 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); nvkm_rd32 239 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); nvkm_rd32 240 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); nvkm_rd32 241 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff; nvkm_rd32 242 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); nvkm_rd32 245 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); nvkm_rd32 246 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; nvkm_rd32 315 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c j = nvkm_rd32(device, 0x1540) & 0xff; nvkm_rd32 392 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_rd32 393 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); nvkm_rd32 394 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200)); nvkm_rd32 395 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204)); nvkm_rd32 410 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200)); nvkm_rd32 411 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204)); nvkm_rd32 414 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200)); nvkm_rd32 415 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204)); nvkm_rd32 418 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200)); nvkm_rd32 419 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204)); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c return nvkm_rd32(gr->engine.subdev.device, 0x1540); nvkm_rd32 244 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04); nvkm_rd32 245 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08); nvkm_rd32 246 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c); nvkm_rd32 247 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e18 = nvkm_rd32(device, ustatus_addr + 0x10); nvkm_rd32 248 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14); nvkm_rd32 249 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18); nvkm_rd32 250 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c); nvkm_rd32 286 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 units = nvkm_rd32(device, 0x1540); nvkm_rd32 298 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c mp10 = nvkm_rd32(device, addr + 0x10); nvkm_rd32 299 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c status = nvkm_rd32(device, addr + 0x14); nvkm_rd32 303 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, addr + 0x20); nvkm_rd32 304 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c pc = nvkm_rd32(device, addr + 0x24); nvkm_rd32 305 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c oplow = nvkm_rd32(device, addr + 0x70); nvkm_rd32 306 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ophigh = nvkm_rd32(device, addr + 0x74); nvkm_rd32 330 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 units = nvkm_rd32(device, 0x1540); nvkm_rd32 342 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ustatus = nvkm_rd32(device, ustatus_addr) & 0x7fffffff; nvkm_rd32 352 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, r)); nvkm_rd32 400 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 status = nvkm_rd32(device, 0x400108); nvkm_rd32 413 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff; nvkm_rd32 422 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 addr = nvkm_rd32(device, 0x400808); nvkm_rd32 425 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 datal = nvkm_rd32(device, 0x40080c); nvkm_rd32 426 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 datah = nvkm_rd32(device, 0x400810); nvkm_rd32 427 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 class = nvkm_rd32(device, 0x400814); nvkm_rd32 428 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 r848 = nvkm_rd32(device, 0x400848); nvkm_rd32 444 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3); nvkm_rd32 450 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 addr = nvkm_rd32(device, 0x40084c); nvkm_rd32 453 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 data = nvkm_rd32(device, 0x40085c); nvkm_rd32 454 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 class = nvkm_rd32(device, 0x400814); nvkm_rd32 486 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff; nvkm_rd32 493 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x406804), nvkm_rd32 494 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x406808), nvkm_rd32 495 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x40680c), nvkm_rd32 496 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x406810)); nvkm_rd32 509 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff; nvkm_rd32 516 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x400c00), nvkm_rd32 517 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x400c08), nvkm_rd32 518 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x400c0c), nvkm_rd32 519 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x400c10)); nvkm_rd32 529 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff; nvkm_rd32 536 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x401804), nvkm_rd32 537 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x401808), nvkm_rd32 538 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x40180c), nvkm_rd32 539 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x401810)); nvkm_rd32 552 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff; nvkm_rd32 560 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x405000), nvkm_rd32 561 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x405004), nvkm_rd32 562 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x405008), nvkm_rd32 563 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x40500c), nvkm_rd32 564 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x405010), nvkm_rd32 565 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x405014), nvkm_rd32 566 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_rd32(device, 0x40501c)); nvkm_rd32 578 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff; nvkm_rd32 626 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 stat = nvkm_rd32(device, 0x400100); nvkm_rd32 627 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff; nvkm_rd32 628 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 addr = nvkm_rd32(device, 0x400704); nvkm_rd32 631 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 data = nvkm_rd32(device, 0x400708); nvkm_rd32 632 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 class = nvkm_rd32(device, 0x400814); nvkm_rd32 647 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 ecode = nvkm_rd32(device, 0x400110); nvkm_rd32 672 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c if (nvkm_rd32(device, 0x400824) & (1 << 31)) nvkm_rd32 673 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_wr32(device, 0x400824, nvkm_rd32(device, 0x400824) & ~(1 << 31)); nvkm_rd32 696 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c units = nvkm_rd32(device, 0x001540); nvkm_rd32 130 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 dma0 = nvkm_rd32(device, 0x700000 + inst); nvkm_rd32 131 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 dma1 = nvkm_rd32(device, 0x700004 + inst); nvkm_rd32 132 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 dma2 = nvkm_rd32(device, 0x700008 + inst); nvkm_rd32 189 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 stat = nvkm_rd32(device, 0x00b100); nvkm_rd32 190 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 type = nvkm_rd32(device, 0x00b230); nvkm_rd32 191 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 mthd = nvkm_rd32(device, 0x00b234); nvkm_rd32 192 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 data = nvkm_rd32(device, 0x00b238); nvkm_rd32 245 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c if (!(nvkm_rd32(device, 0x00b200) & 0x00000001)) nvkm_rd32 249 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_rd32(device, 0x00b200)); nvkm_rd32 77 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c if (nvkm_rd32(device, 0x00b318) == inst) nvkm_rd32 150 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff; nvkm_rd32 151 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c u32 stat = nvkm_rd32(device, 0x00b100); nvkm_rd32 152 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c u32 type = nvkm_rd32(device, 0x00b230); nvkm_rd32 153 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c u32 mthd = nvkm_rd32(device, 0x00b234); nvkm_rd32 154 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c u32 data = nvkm_rd32(device, 0x00b238); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c u32 stat = nvkm_rd32(device, 0x00b100); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c u32 type = nvkm_rd32(device, 0x00b230); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c u32 mthd = nvkm_rd32(device, 0x00b234); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c u32 data = nvkm_rd32(device, 0x00b238); nvkm_rd32 109 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c if (!(nvkm_rd32(device, 0x00b200) & 0x00000001)) nvkm_rd32 113 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c nvkm_rd32(device, 0x00b200)); nvkm_rd32 152 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 0: ctr->ctr = nvkm_rd32(device, dom->addr + 0x08c); break; nvkm_rd32 153 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 1: ctr->ctr = nvkm_rd32(device, dom->addr + 0x088); break; nvkm_rd32 154 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 2: ctr->ctr = nvkm_rd32(device, dom->addr + 0x080); break; nvkm_rd32 155 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 3: ctr->ctr = nvkm_rd32(device, dom->addr + 0x090); break; nvkm_rd32 157 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c dom->clk = nvkm_rd32(device, dom->addr + 0x070); nvkm_rd32 210 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask = (1 << nvkm_rd32(device, 0x022430)) - 1; nvkm_rd32 211 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x022504); nvkm_rd32 212 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x022584); nvkm_rd32 220 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask = (1 << nvkm_rd32(device, 0x022438)) - 1; nvkm_rd32 221 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x022548); nvkm_rd32 222 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x0225c8); nvkm_rd32 50 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 0: ctr->ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break; nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 1: ctr->ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break; nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 2: ctr->ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break; nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 3: ctr->ctr = nvkm_rd32(device, 0x00a740 + dom->addr); break; nvkm_rd32 55 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c dom->clk = nvkm_rd32(device, 0x00a600 + dom->addr); nvkm_rd32 47 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c u32 ssta = nvkm_rd32(device, 0x087040) & 0x0000ffff; nvkm_rd32 48 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c u32 addr = nvkm_rd32(device, 0x087040) >> 16; nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c u32 data = nvkm_rd32(device, 0x087044); nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c u32 disp = nvkm_rd32(device, sec2->addr + 0x01c); nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c u32 intr = nvkm_rd32(device, sec2->addr + 0x008) & disp & ~(disp >> 16); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 unk104 = nvkm_rd32(device, base + 0xd04); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 intr = nvkm_rd32(device, base + 0xc20); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 chan = nvkm_rd32(device, base + 0xc28); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 unk10c = nvkm_rd32(device, base + 0xd0c); nvkm_rd32 71 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c intr = nvkm_rd32(device, base + 0xc20); nvkm_rd32 151 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c tmp = nvkm_rd32(device, 0x0); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c if (!(nvkm_rd32(device, 0x070000) & 0x00000002)) nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c if (!(nvkm_rd32(device, 0x001710) & 0x00000003)) nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c if (!(nvkm_rd32(device, 0x001710) & 0x0000000c)) nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c if (!(nvkm_rd32(device, 0x00330c) & 0x00000002)) nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c if (!(nvkm_rd32(device, 0xb80f50) & 0x0000000c)) nvkm_rd32 59 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c if (!(nvkm_rd32(device, 0xb80f50) & 0x00000003)) nvkm_rd32 187 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return nvkm_rd32(device, reg); nvkm_rd32 206 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 tmp = nvkm_rd32(device, reg); nvkm_rd32 390 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c u32 sel_clk = nvkm_rd32(device, 0x680524); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c return (nvkm_rd32(subdev->device, 0x101000) & 0x0000003c) >> 2; nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c *(u32 *)&bios->data[i] = nvkm_rd32(device, 0x700000 + i); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c addr = nvkm_rd32(device, 0x021c04); nvkm_rd32 71 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c addr = nvkm_rd32(device, 0x022500); nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c addr = nvkm_rd32(device, 0x625f04); nvkm_rd32 84 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c addr = nvkm_rd32(device, 0x619f04); nvkm_rd32 97 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c addr = (u64)nvkm_rd32(device, 0x001700) << 16; nvkm_rd32 108 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c priv->bar0 = nvkm_rd32(device, 0x001700); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c *(u32 *)&bios->data[i] = nvkm_rd32(device, 0x300000 + i); nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c u32 addr = nvkm_rd32(device, 0x009084); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c u32 data = nvkm_rd32(device, 0x009088); nvkm_rd32 142 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c heads = nvkm_rd32(device, 0x610050); nvkm_rd32 146 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c x = nvkm_rd32(device, 0x610b40 + (0x540 * i)); nvkm_rd32 90 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h reg->data = nvkm_rd32(device, reg->addr); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c u32 gpio = nvkm_rd32(device, 0x001104) & nvkm_rd32(device, 0x001144); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c u32 addr = nvkm_rd32(device, 0x009084); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c u32 data = nvkm_rd32(device, 0x009088); nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) nvkm_rd32 57 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); nvkm_rd32 60 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c u32 addr = nvkm_rd32(device, 0x009084); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c u32 data = nvkm_rd32(device, 0x009088); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 ssrc = nvkm_rd32(device, dsrc); nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 ctrl = nvkm_rd32(device, pll + 0x00); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 coef = nvkm_rd32(device, pll + 0x04); nvkm_rd32 101 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4)); nvkm_rd32 116 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sctl = nvkm_rd32(device, dctl + (doff * 4)); nvkm_rd32 136 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); nvkm_rd32 137 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 ssel = nvkm_rd32(device, 0x137100); nvkm_rd32 183 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c if (nvkm_rd32(device, 0x1373f0) & 0x00000002) nvkm_rd32 360 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) nvkm_rd32 381 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c if (nvkm_rd32(device, addr + 0x00) & 0x00020000) nvkm_rd32 400 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 ssrc = nvkm_rd32(device, dsrc); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 ctrl = nvkm_rd32(device, pll + 0x00); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 coef = nvkm_rd32(device, pll + 0x04); nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c fN = nvkm_rd32(device, pll + 0x10) >> 16; nvkm_rd32 109 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4)); nvkm_rd32 110 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 sctl = nvkm_rd32(device, dctl + (doff * 4)); nvkm_rd32 136 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) { nvkm_rd32 148 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); nvkm_rd32 152 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 ssel = nvkm_rd32(device, 0x137100); nvkm_rd32 161 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04)); nvkm_rd32 373 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) nvkm_rd32 400 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c if (nvkm_rd32(device, addr + 0x00) & 0x00020000) nvkm_rd32 429 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = nvkm_rd32(device, GPCPLL_COEFF); nvkm_rd32 250 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); nvkm_rd32 262 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 265 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 292 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 311 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_rd32(device, GPC2CLK_OUT); nvkm_rd32 329 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_rd32(device, GPC2CLK_OUT); nvkm_rd32 574 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h val = nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 167 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c val = nvkm_rd32(device, GPCPLL_CFG2); nvkm_rd32 316 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); nvkm_rd32 327 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 335 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 356 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 385 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPC2CLK_OUT); nvkm_rd32 427 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPC2CLK_OUT); nvkm_rd32 540 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c val = nvkm_rd32(device, GPCPLL_DVFS1); nvkm_rd32 786 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c data = nvkm_rd32(device, GPCPLL_CFG3) >> nvkm_rd32 821 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_rd32(device, GPCPLL_CFG); nvkm_rd32 837 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c data = nvkm_rd32(device, 0x021944); nvkm_rd32 842 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c data = nvkm_rd32(device, 0x021948); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 sctl = nvkm_rd32(device, 0x4120 + (idx * 4)); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c return nvkm_rd32(device, 0x00471c) * 1000; nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c sctl = nvkm_rd32(device, 0x4120 + (idx * 4)); nvkm_rd32 111 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 ctrl = nvkm_rd32(device, pll + 0); nvkm_rd32 117 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 coef = nvkm_rd32(device, pll + 4); nvkm_rd32 167 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c hsrc = (nvkm_rd32(device, 0xc040) & 0x30000000) >> 28; nvkm_rd32 317 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (!nvkm_rd32(device, 0x000100)) nvkm_rd32 326 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (nvkm_rd32(device, 0x002504) & 0x00000010) nvkm_rd32 332 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 tmp = nvkm_rd32(device, 0x00251c) & 0x0000003f; nvkm_rd32 375 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c bypass = nvkm_rd32(device, ctrl) & 0x00000008; nvkm_rd32 387 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (nvkm_rd32(device, ctrl) & 0x00020000) nvkm_rd32 419 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 hsrc = (nvkm_rd32(device, 0xc040)); nvkm_rd32 447 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 fb_delay = nvkm_rd32(device, 0x10002c); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_rd32(device, 0x004600); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 ctrl = nvkm_rd32(device, base + 0); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 coef = nvkm_rd32(device, base + 4); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 mast = nvkm_rd32(device, 0x00c054); nvkm_rd32 107 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; nvkm_rd32 130 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; nvkm_rd32 357 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 tmp = nvkm_rd32(device, 0x004080) & pllmask; nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 ctrl = nvkm_rd32(device, reg + 0x00); nvkm_rd32 59 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 ctrl = nvkm_rd32(device, reg + 0x00); nvkm_rd32 60 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 coef = nvkm_rd32(device, reg + 0x04); nvkm_rd32 102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 mast = nvkm_rd32(device, 0x00c040); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_rd32(device, 0x004700); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_rd32(device, 0x004800); nvkm_rd32 57 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 rsel = nvkm_rd32(device, 0x00e18c); nvkm_rd32 73 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c coef = nvkm_rd32(device, 0x00e81c); nvkm_rd32 90 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c rsel = nvkm_rd32(device, 0x00c050); nvkm_rd32 108 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c coef = nvkm_rd32(device, 0x00e81c + (id * 0x28)); nvkm_rd32 109 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c P = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7; nvkm_rd32 129 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 src, mast = nvkm_rd32(device, 0x00c040); nvkm_rd32 161 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 mast = nvkm_rd32(device, 0x00c040); nvkm_rd32 162 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 ctrl = nvkm_rd32(device, base + 0); nvkm_rd32 163 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 coef = nvkm_rd32(device, base + 4); nvkm_rd32 197 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 mast = nvkm_rd32(device, 0x00c040); nvkm_rd32 221 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; nvkm_rd32 230 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; nvkm_rd32 242 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c P = (nvkm_rd32(device, 0x004008) & 0x00070000) >> 16; nvkm_rd32 243 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (nvkm_rd32(device, 0x004008) & 0x00000200) { nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c u32 r001540 = nvkm_rd32(device, 0x001540); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c u32 r00154c = nvkm_rd32(device, 0x00154c); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c u32 r001540 = nvkm_rd32(device, 0x001540); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c u32 r00154c = nvkm_rd32(device, 0x00154c); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c u32 r022500 = nvkm_rd32(device, 0x022500); nvkm_rd32 104 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c base->post = ((nvkm_rd32(device, 0x2240c) & BIT(1)) == 0); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c u32 r021c00 = nvkm_rd32(device, 0x021c00); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c u32 r021c04 = nvkm_rd32(device, 0x021c04); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c nvkm_wr32(device, 0x10a1c0, nvkm_rd32(device, 0x10a1c4) + argi); nvkm_rd32 69 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c return nvkm_rd32(device, 0x10a1c4); nvkm_rd32 162 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c if (nvkm_rd32(device, 0x10a040) & 0x00002000) nvkm_rd32 69 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c u32 r001540 = nvkm_rd32(device, 0x001540); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c u32 r00154c = nvkm_rd32(device, 0x00154c); nvkm_rd32 127 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c init->r001540 = nvkm_rd32(device, 0x001540); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c u32 r001540 = nvkm_rd32(device, 0x001540); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c u32 r00154c = nvkm_rd32(device, 0x00154c); nvkm_rd32 148 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll = nvkm_rd32(device, reg); nvkm_rd32 158 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c saved_powerctrl_1 = nvkm_rd32(device, 0x001584); nvkm_rd32 175 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_rd32(device, reg); nvkm_rd32 205 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll1 = nvkm_rd32(device, reg1); nvkm_rd32 206 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0; nvkm_rd32 221 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c oldramdac580 = nvkm_rd32(device, 0x680580); nvkm_rd32 237 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c saved_powerctrl_1 = nvkm_rd32(device, 0x001584); nvkm_rd32 257 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c savedc040 = nvkm_rd32(device, 0xc040); nvkm_rd32 289 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldPval = nvkm_rd32(device, Preg); nvkm_rd32 298 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) nvkm_rd32 318 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c saved4600 = nvkm_rd32(device, 0x4600); nvkm_rd32 332 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c savedc040 = nvkm_rd32(device, 0xc040); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2; nvkm_rd32 75 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c if (nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) nvkm_rd32 106 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c v = nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; nvkm_rd32 78 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c int off = nvkm_rd32(device, 0x10020c) - 0x100000; nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c amount = nvkm_rd32(device, 0x10020c); nvkm_rd32 57 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c amount = nvkm_rd32(device, 0x10020c); nvkm_rd32 84 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c u32 r001540 = nvkm_rd32(device, 0x001540); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c buffer->entries = nvkm_rd32(buffer->fault->subdev.device, 0x002a78); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c u32 get = nvkm_rd32(device, buffer->get); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c u32 put = nvkm_rd32(device, buffer->put); nvkm_rd32 112 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c buffer->entries = nvkm_rd32(device, 0x100e34 + foff) & 0x000fffff; nvkm_rd32 131 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 addrlo = nvkm_rd32(device, 0x100e4c); nvkm_rd32 132 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 addrhi = nvkm_rd32(device, 0x100e50); nvkm_rd32 133 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 info0 = nvkm_rd32(device, 0x100e54); nvkm_rd32 134 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 insthi = nvkm_rd32(device, 0x100e58); nvkm_rd32 135 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 info1 = nvkm_rd32(device, 0x100e5c); nvkm_rd32 156 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c u32 stat = nvkm_rd32(device, 0x100a20); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c buffer->entries = nvkm_rd32(device, 0xb83010 + foff) & 0x000fffff; nvkm_rd32 78 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 addrlo = nvkm_rd32(device, 0xb83080); nvkm_rd32 79 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 addrhi = nvkm_rd32(device, 0xb83084); nvkm_rd32 80 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 info0 = nvkm_rd32(device, 0xb83088); nvkm_rd32 81 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 insthi = nvkm_rd32(device, 0xb8308c); nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 info1 = nvkm_rd32(device, 0xb83090); nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c u32 stat = nvkm_rd32(device, 0xb83094); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c const u8 ramcfg = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2; nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c u32 intr = nvkm_rd32(device, 0x000100); nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c nvkm_wr32(device, 0x1fac80, nvkm_rd32(device, 0x100c80)); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c nvkm_wr32(device, 0x1facc4, nvkm_rd32(device, 0x100cc4)); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c nvkm_wr32(device, 0x1facc8, nvkm_rd32(device, 0x100cc8)); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c nvkm_wr32(device, 0x1faccc, nvkm_rd32(device, 0x100ccc)); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c nvkm_rd32(device, 0x100240 + (i * 0x10)); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nvkm_rd32(device, 0x100240 + (i * 0x10)); nvkm_rd32 83 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c const u32 tags = nvkm_rd32(fb->subdev.device, 0x100320); nvkm_rd32 70 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >> nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c int l = nvkm_rd32(device, 0x1003d0); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c nvkm_rd32(device, 0x100600 + (i * 0x10)); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c nvkm_rd32(device, 0x100600 + (i * 0x10)); nvkm_rd32 148 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c idx = nvkm_rd32(device, 0x100c90); nvkm_rd32 155 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c trap[i] = nvkm_rd32(device, 0x100c94); nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h reg->data = nvkm_rd32(device, reg->addr); nvkm_rd32 112 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c u32 part = nvkm_rd32(device, 0x022438), i; nvkm_rd32 113 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c u32 mask = nvkm_rd32(device, 0x022554); nvkm_rd32 468 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c return nvkm_rd32(device, 0x11020c + (fbpa * 0x1000)); nvkm_rd32 486 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c u32 fbpao = nvkm_rd32(device, 0x022554); nvkm_rd32 500 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c u32 fbps = nvkm_rd32(device, 0x022438); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c u32 fbpt = nvkm_rd32(device, 0x022438); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c u32 fbpat = nvkm_rd32(device, 0x02243c); nvkm_rd32 242 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 prev = nvkm_rd32(device, addr); nvkm_rd32 1423 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c save = nvkm_rd32(device, 0x10f65c) & 0x000000f0; nvkm_rd32 1548 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->parts = nvkm_rd32(device, 0x022438); nvkm_rd32 1549 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->pmask = nvkm_rd32(device, 0x022554); nvkm_rd32 1553 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000)); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c u32 fbpao = nvkm_rd32(device, 0x021c14); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c u32 ltcs = nvkm_rd32(device, 0x022450); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c u32 fbpas = nvkm_rd32(device, 0x022458); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c if (!(nvkm_rd32(device, 0x021d38) & BIT(fbp))) { nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c u32 ltco = nvkm_rd32(device, 0x021d70 + (fbp * 4)); nvkm_rd32 58 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c u32 save = nvkm_rd32(device, 0x9a065c) & 0x000000f0; nvkm_rd32 77 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c return nvkm_rd32(device, 0x90020c + (fbpa * 0x4000)); nvkm_rd32 323 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c r001700 = nvkm_rd32(device, 0x1700); nvkm_rd32 331 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c train->r_100720 = nvkm_rd32(device, 0x100720); nvkm_rd32 332 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c train->r_1111e0 = nvkm_rd32(device, 0x1111e0); nvkm_rd32 333 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c train->r_111400 = nvkm_rd32(device, 0x111400); nvkm_rd32 356 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c cur2 = nvkm_rd32(device, 0x100228); nvkm_rd32 357 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c cur3 = nvkm_rd32(device, 0x10022c); nvkm_rd32 358 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c cur7 = nvkm_rd32(device, 0x10023c); nvkm_rd32 359 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c cur8 = nvkm_rd32(device, 0x100240); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c u64 base = (u64)nvkm_rd32(device, 0x100e10) << 12; nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c u64 size = (u64)nvkm_rd32(device, 0x100e14) << 12; nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c u32 boot0 = nvkm_rd32(device, NV04_PFB_BOOT_0); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c u32 cfg0 = nvkm_rd32(device, 0x100200); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c u32 pbus1218 = nvkm_rd32(device, 0x001218); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c u32 size = (nvkm_rd32(device, 0x10020c) & 0xff000000); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; nvkm_rd32 80 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); nvkm_rd32 83 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) { nvkm_rd32 100 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); nvkm_rd32 106 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); nvkm_rd32 166 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); nvkm_rd32 205 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u32 pbus1218 = nvkm_rd32(device, 0x001218); nvkm_rd32 206 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; nvkm_rd32 221 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c u32 fb474 = nvkm_rd32(device, 0x100474); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c u32 fb474 = nvkm_rd32(device, 0x100474); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c u32 fb914 = nvkm_rd32(device, 0x100914); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; nvkm_rd32 81 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c cur2 = nvkm_rd32(device, 0x100228); nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c cur4 = nvkm_rd32(device, 0x100230); nvkm_rd32 83 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c cur7 = nvkm_rd32(device, 0x10023c); nvkm_rd32 84 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c cur8 = nvkm_rd32(device, 0x100240); nvkm_rd32 159 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[i] = nvkm_rd32(device, 0x100220 + (i * 4)); nvkm_rd32 512 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c r0 = nvkm_rd32(device, 0x100200); nvkm_rd32 513 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c r4 = nvkm_rd32(device, 0x100204); nvkm_rd32 514 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c rt = nvkm_rd32(device, 0x100250); nvkm_rd32 516 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c r0, r4, rt, nvkm_rd32(device, 0x001540)); nvkm_rd32 549 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c u64 size = nvkm_rd32(device, 0x10020c); nvkm_rd32 553 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c switch (nvkm_rd32(device, 0x100714) & 0x00000007) { nvkm_rd32 574 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; nvkm_rd32 576 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1; nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c val = nvkm_rd32(device, 0x021100 + addr); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c return nvkm_rd32(device, 0x021100 + addr); nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c val = nvkm_rd32(device, 0x021000 + addr); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c u32 intr0 = nvkm_rd32(device, 0x00e054); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c u32 intr1 = nvkm_rd32(device, 0x00e074); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c u32 stat0 = nvkm_rd32(device, 0x00e050) & intr0; nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c u32 stat1 = nvkm_rd32(device, 0x00e070) & intr1; nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c u32 inte0 = nvkm_rd32(device, 0x00e050); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c u32 inte1 = nvkm_rd32(device, 0x00e070); nvkm_rd32 69 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c return !!(nvkm_rd32(device, 0x00d610 + (line * 4)) & 0x00004000); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c u32 intr0 = nvkm_rd32(device, 0x00dc00); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c u32 intr1 = nvkm_rd32(device, 0x00dc80); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c u32 stat0 = nvkm_rd32(device, 0x00dc08) & intr0; nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c u32 stat1 = nvkm_rd32(device, 0x00dc88) & intr1; nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c u32 inte0 = nvkm_rd32(device, 0x00dc08); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c u32 inte1 = nvkm_rd32(device, 0x00dc88); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c line = nvkm_rd32(device, 0x600818) >> line; nvkm_rd32 39 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c line = nvkm_rd32(device, 0x60081c) >> line; nvkm_rd32 44 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c line = nvkm_rd32(device, 0x600850) >> line; nvkm_rd32 86 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c u32 intr = nvkm_rd32(device, 0x001104); nvkm_rd32 87 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c u32 stat = nvkm_rd32(device, 0x001144) & intr; nvkm_rd32 97 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c u32 inte = nvkm_rd32(device, 0x001144); nvkm_rd32 92 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c return !!(nvkm_rd32(device, reg) & (4 << shift)); nvkm_rd32 99 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 intr = nvkm_rd32(device, 0x00e054); nvkm_rd32 100 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 stat = nvkm_rd32(device, 0x00e050) & intr; nvkm_rd32 110 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 inte = nvkm_rd32(device, 0x00e050); nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50)); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50)); nvkm_rd32 92 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c stat = nvkm_rd32(device, 0x00e4e8 + base); nvkm_rd32 107 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c ctrl = nvkm_rd32(device, 0x00e4e4 + base); nvkm_rd32 126 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c ctrl = nvkm_rd32(device, 0x00e4e4 + base); nvkm_rd32 151 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c xbuf[i / 4] = nvkm_rd32(device, 0x00e4d0 + base + i); nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); nvkm_rd32 92 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c stat = nvkm_rd32(device, 0x00d958 + base); nvkm_rd32 107 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c ctrl = nvkm_rd32(device, 0x00d954 + base); nvkm_rd32 126 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c ctrl = nvkm_rd32(device, 0x00d954 + base); nvkm_rd32 151 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c xbuf[i / 4] = nvkm_rd32(device, 0x00d940 + base + i); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c return !!(nvkm_rd32(device, bus->addr) & 0x00000010); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c return !!(nvkm_rd32(device, bus->addr) & 0x00000020); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c return !!(nvkm_rd32(device, bus->addr) & 0x00040000); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c return !!(nvkm_rd32(device, bus->addr) & 0x00080000); nvkm_rd32 60 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c return !!(nvkm_rd32(device, bus->addr) & 0x00000001); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c return !!(nvkm_rd32(device, bus->addr) & 0x00000002); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c u32 intr = nvkm_rd32(device, 0x00e06c); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c u32 stat = nvkm_rd32(device, 0x00e068) & intr, i; nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c u32 temp = nvkm_rd32(device, 0x00e068), i; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c u32 intr = nvkm_rd32(device, 0x00dc60); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c u32 stat = nvkm_rd32(device, 0x00dc68) & intr, i; nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c u32 temp = nvkm_rd32(device, 0x00dc68), i; nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); nvkm_rd32 42 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 intr0 = nvkm_rd32(device, 0x121c58); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 intr1 = nvkm_rd32(device, 0x121c5c); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 hubnr = nvkm_rd32(device, 0x121c70); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 ropnr = nvkm_rd32(device, 0x121c74); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c u32 gpcnr = nvkm_rd32(device, 0x121c78); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); nvkm_rd32 42 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); nvkm_rd32 53 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); nvkm_rd32 54 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 intr0 = nvkm_rd32(device, 0x120058); nvkm_rd32 64 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 intr1 = nvkm_rd32(device, 0x12005c); nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 hubnr = nvkm_rd32(device, 0x120070); nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 ropnr = nvkm_rd32(device, 0x120074); nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c u32 gpcnr = nvkm_rd32(device, 0x120078); nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c nvkm_rd32(device, 0x122204); nvkm_rd32 52 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c u32 status0 = nvkm_rd32(device, 0x120058); nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c if (!(nvkm_rd32(device, 0x12004c) & 0x0000003f)) nvkm_rd32 36 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gp10b.c nvkm_rd32(device, 0x122204); nvkm_rd32 58 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); nvkm_rd32 149 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c return nvkm_rd32(imem->subdev.device, 0x700000 + addr); nvkm_rd32 169 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8); nvkm_rd32 90 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c data = nvkm_rd32(device, 0x700000 + addr); nvkm_rd32 48 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c if (!nvkm_rd32(device, addr)) nvkm_rd32 98 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 intr = nvkm_rd32(device, base + 0x020); nvkm_rd32 116 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c mask = nvkm_rd32(device, 0x00017c); nvkm_rd32 159 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 bits = (nvkm_rd32(device, 0x100c80) & 0x00001000) ? 16 : 17; nvkm_rd32 211 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c const u32 parts = nvkm_rd32(device, 0x022438); nvkm_rd32 212 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c const u32 mask = nvkm_rd32(device, 0x022554); nvkm_rd32 213 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28; nvkm_rd32 229 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); nvkm_rd32 77 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c u32 intr = nvkm_rd32(device, base + 0x00c); nvkm_rd32 95 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c mask = nvkm_rd32(device, 0x00017c); nvkm_rd32 108 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c const u32 parts = nvkm_rd32(device, 0x022438); nvkm_rd32 109 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c const u32 mask = nvkm_rd32(device, 0x021c14); nvkm_rd32 110 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c const u32 slice = nvkm_rd32(device, 0x17e280) >> 28; nvkm_rd32 126 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); nvkm_rd32 34 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c ltc->ltc_nr = nvkm_rd32(device, 0x12006c); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c mask = nvkm_rd32(device, 0x0001c0); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c ltc->ltc_nr = nvkm_rd32(device, 0x12006c); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; nvkm_rd32 145 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_rd32(device, 0x000200); nvkm_rd32 163 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_rd32(device, 0x000200); nvkm_rd32 173 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c ((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable); nvkm_rd32 68 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c nvkm_rd32(device, 0x000140); nvkm_rd32 83 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c u32 intr0 = nvkm_rd32(device, 0x000100); nvkm_rd32 84 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c u32 intr1 = nvkm_rd32(device, 0x000104); nvkm_rd32 48 drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c nvkm_rd32(device, 0x000140); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c return nvkm_rd32(mc->subdev.device, 0x000100); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c u32 tmp = nvkm_rd32(device, 0x10020c); nvkm_rd32 28 drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c u32 stat = nvkm_rd32(device, 0xb81010); nvkm_rd32 42 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c addr = nvkm_rd32(device, 0x10020c); nvkm_rd32 200 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c if (nvkm_rd32(device, 0x100c80) & 0x00ff0000) nvkm_rd32 222 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c if (nvkm_rd32(device, 0x100c80) & 0x00008000) nvkm_rd32 89 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c if (nvkm_rd32(device, 0x100810) & 0x00000020) nvkm_rd32 191 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c if (nvkm_rd32(device, 0x100808) & 0x00000001) nvkm_rd32 217 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c if (!(nvkm_rd32(device, 0xb830b0) & 0x80000000)) nvkm_rd32 39 drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c return (nvkm_rd32(device, 0x00154c) & 0x1) + 1; nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c return (nvkm_rd32(device, 0x02241c) & 0x1) + 1; nvkm_rd32 57 drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c u8 punits_pci_cap_speed = nvkm_rd32(device, 0x02241c) & 0x80; nvkm_rd32 29 drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c return (nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x4) == 0x4 ? 2 : 1; nvkm_rd32 62 drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c int speed2 = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x30000; nvkm_rd32 114 drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c u32 max_speed = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x300000; nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c return nvkm_rd32(device, 0x001800 + addr); nvkm_rd32 30 drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c return nvkm_rd32(device, 0x088000 + addr); nvkm_rd32 102 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c if (!nvkm_rd32(device, 0x10a04c)) nvkm_rd32 112 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c if (!(nvkm_rd32(device, 0x10a10c) & 0x00000006)) nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c if (nvkm_rd32(device, 0x00c800) & 0x40000000) { nvkm_rd32 65 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c nvkm_rd32(device, 0x000200); nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c nvkm_rd32(device, 0x000200); nvkm_rd32 59 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c nvkm_rd32(device, 0x000200); nvkm_rd32 71 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c if (!(nvkm_rd32(device, magic[i].addr) & 0x80000000)) nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c nvkm_rd32(device, 0x000200); nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c return !(nvkm_rd32(pmu->subdev.device, 0x10a3c0) & 0x00000001); nvkm_rd32 39 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c addr = nvkm_rd32(device, 0x10a4a0); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 tmp = nvkm_rd32(device, 0x10a4b0); nvkm_rd32 61 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c } while (nvkm_rd32(device, 0x10a580) != 0x00000001); nvkm_rd32 94 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 addr = nvkm_rd32(device, 0x10a4cc); nvkm_rd32 95 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c if (addr == nvkm_rd32(device, 0x10a4c8)) nvkm_rd32 101 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c } while (nvkm_rd32(device, 0x10a580) != 0x00000002); nvkm_rd32 106 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c process = nvkm_rd32(device, 0x10a1c4); nvkm_rd32 107 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c message = nvkm_rd32(device, 0x10a1c4); nvkm_rd32 108 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c data0 = nvkm_rd32(device, 0x10a1c4); nvkm_rd32 109 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c data1 = nvkm_rd32(device, 0x10a1c4); nvkm_rd32 143 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 disp = nvkm_rd32(device, 0x10a01c); nvkm_rd32 144 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); nvkm_rd32 147 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 stat = nvkm_rd32(device, 0x10a16c); nvkm_rd32 151 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c nvkm_rd32(device, 0x10a168)); nvkm_rd32 165 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c nvkm_rd32(device, 0x10a7a0), nvkm_rd32 166 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c nvkm_rd32(device, 0x10a7a4)); nvkm_rd32 189 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c nvkm_rd32(device, 0x022210); nvkm_rd32 195 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c return nvkm_rd32(pmu->subdev.device, 0x022210) & 0x00000001; nvkm_rd32 224 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c if (nvkm_rd32(device, 0x10a4d0)) nvkm_rd32 228 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->send.base = nvkm_rd32(device, 0x10a4d0) & 0x0000ffff; nvkm_rd32 229 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->send.size = nvkm_rd32(device, 0x10a4d0) >> 16; nvkm_rd32 233 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c if (nvkm_rd32(device, 0x10a4dc)) nvkm_rd32 237 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->recv.base = nvkm_rd32(device, 0x10a4dc) & 0x0000ffff; nvkm_rd32 238 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->recv.size = nvkm_rd32(device, 0x10a4dc) >> 16; nvkm_rd32 66 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c } while (nvkm_rd32(device, 0x10a580) != 0x00000003); nvkm_rd32 84 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c finish = nvkm_rd32(device, 0x10a1c0) & 0x00ffffff; nvkm_rd32 133 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c heads = nvkm_rd32(device, 0x610050); nvkm_rd32 137 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c x = nvkm_rd32(device, 0x610b40 + (0x540 * i)); nvkm_rd32 186 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c res[i] = nvkm_rd32(device, 0x10a1c4); nvkm_rd32 885 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c wpr_lo = (nvkm_rd32(device, 0x100cd4) & ~0xff); nvkm_rd32 888 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c wpr_hi = (nvkm_rd32(device, 0x100cd4) & ~0xff); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c reg = nvkm_rd32(device, 0x100cd0); nvkm_rd32 35 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c return nvkm_rd32(device, 0x20400); nvkm_rd32 106 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c temp = nvkm_rd32(device, thrs_reg); nvkm_rd32 149 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c intr = nvkm_rd32(device, 0x20100) & 0x3ff; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c u32 gpio = nvkm_rd32(device, 0x00d610 + (line * 0x04)); nvkm_rd32 74 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c if (nvkm_rd32(device, 0x00d610 + (line * 0x04)) & 0x00000040) { nvkm_rd32 75 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c *divs = nvkm_rd32(device, 0x00e114 + (indx * 8)); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c *duty = nvkm_rd32(device, 0x00e118 + (indx * 8)); nvkm_rd32 80 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff; nvkm_rd32 81 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c *duty = nvkm_rd32(device, 0x0200dc) & 0x1fff; nvkm_rd32 37 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; nvkm_rd32 38 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c *duty = nvkm_rd32(device, 0x10eb24) & 0x1fff; nvkm_rd32 31 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c u32 tsensor = nvkm_rd32(device, 0x020460); nvkm_rd32 32 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c u32 tach = nvkm_rd32(device, 0x00e728) & 0x0000ffff; nvkm_rd32 33 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c u32 ctrl = nvkm_rd32(device, 0x00e720); nvkm_rd32 63 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c return nvkm_rd32(device, 0x15b4) & 0x3fff; nvkm_rd32 67 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c return nvkm_rd32(device, 0x15b4) & 0xff; nvkm_rd32 82 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c core_temp = nvkm_rd32(device, 0x15b4) & 0x3fff; nvkm_rd32 85 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c core_temp = nvkm_rd32(device, 0x15b4) & 0xff; nvkm_rd32 126 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c u32 reg = nvkm_rd32(device, 0x0010f0); nvkm_rd32 134 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c u32 reg = nvkm_rd32(device, 0x0015f4); nvkm_rd32 136 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c *divs = nvkm_rd32(device, 0x0015f8); nvkm_rd32 172 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c uint32_t stat = nvkm_rd32(device, 0x1100); nvkm_rd32 73 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c if (nvkm_rd32(device, ctrl) & (1 << line)) { nvkm_rd32 74 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c *divs = nvkm_rd32(device, 0x00e114 + (id * 8)); nvkm_rd32 75 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c *duty = nvkm_rd32(device, 0x00e118 + (id * 8)); nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c u8 pwm_div = nvkm_rd32(device, 0x410c); nvkm_rd32 104 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c if (nvkm_rd32(device, 0xc040) & 0x800000) { nvkm_rd32 135 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c core_temp = nvkm_rd32(device, 0x20014) & 0x3fff; nvkm_rd32 49 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c hi = nvkm_rd32(device, NV04_PTIMER_TIME_1); nvkm_rd32 50 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c lo = nvkm_rd32(device, NV04_PTIMER_TIME_0); nvkm_rd32 51 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c } while (hi != nvkm_rd32(device, NV04_PTIMER_TIME_1)); nvkm_rd32 76 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c u32 stat = nvkm_rd32(device, NV04_PTIMER_INTR_0); nvkm_rd32 103 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR); nvkm_rd32 104 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR); nvkm_rd32 40 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR); nvkm_rd32 41 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR); nvkm_rd32 43 drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c data = nvkm_rd32(device, 0x022700 + (i * 0x04)); nvkm_rd32 45 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c div = nvkm_rd32(device, 0x20340); nvkm_rd32 46 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c duty = nvkm_rd32(device, 0x20344);