nvkm_devidx 9 drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h enum nvkm_devidx index; nvkm_devidx 11 drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h void nvkm_mc_enable(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 12 drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h void nvkm_mc_disable(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 13 drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 14 drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h void nvkm_mc_reset(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 18 drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h void nvkm_mc_intr_mask(struct nvkm_device *, enum nvkm_devidx, bool enable); nvkm_devidx 12 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h u32 nvkm_top_addr(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 13 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 15 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 16 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_devidx); nvkm_devidx 17 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h enum nvkm_devidx nvkm_top_fault(struct nvkm_device *, int fault); nvkm_devidx 18 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); nvkm_devidx 46 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c enum nvkm_devidx subidx; nvkm_devidx 505 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c enum nvkm_devidx engidx = nvkm_top_fault(device, info->engine); nvkm_devidx 910 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c enum nvkm_devidx engidx; nvkm_devidx 90 drivers/gpu/drm/nouveau/nvkm/falcon/base.c enum nvkm_devidx id = falcon->owner->index; nvkm_devidx 107 drivers/gpu/drm/nouveau/nvkm/falcon/base.c enum nvkm_devidx id = falcon->owner->index; nvkm_devidx 38 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mc_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx, bool en) nvkm_devidx 92 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c enum nvkm_devidx subidx = __ffs64(subdevs); nvkm_devidx 118 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c enum nvkm_devidx devidx) nvkm_devidx 139 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx) nvkm_devidx 150 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mc_disable(struct nvkm_device *device, enum nvkm_devidx devidx) nvkm_devidx 158 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx) nvkm_devidx 168 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_devidx devidx) nvkm_devidx 34 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h enum nvkm_devidx engine; nvkm_devidx 44 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c nvkm_top_addr(struct nvkm_device *device, enum nvkm_devidx index) nvkm_devidx 60 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) nvkm_devidx 76 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) nvkm_devidx 115 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_devidx devidx) nvkm_devidx 128 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c enum nvkm_devidx nvkm_devidx 142 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c enum nvkm_devidx nvkm_devidx 15 drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h enum nvkm_devidx index;