nvkm_clk_read 122 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); nvkm_clk_read 120 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c lo = max(nvkm_clk_read(clk, domain->name), 0); nvkm_clk_read 602 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c ret = nvkm_clk_read(clk, clock->name); nvkm_clk_read 54 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); nvkm_clk_read 55 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); nvkm_clk_read 79 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); nvkm_clk_read 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); nvkm_clk_read 184 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_mpll); nvkm_clk_read 185 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_mdiv); nvkm_clk_read 601 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_freq = nvkm_clk_read(&clk->base.base, nv_clk_src_gpc); nvkm_clk_read 54 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 95 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; nvkm_clk_read 97 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; nvkm_clk_read 100 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); nvkm_clk_read 102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); nvkm_clk_read 103 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk); nvkm_clk_read 110 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nvkm_clk_read 112 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P; nvkm_clk_read 118 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_core); nvkm_clk_read 121 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_core); nvkm_clk_read 124 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); nvkm_clk_read 126 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); nvkm_clk_read 134 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; nvkm_clk_read 135 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nvkm_clk_read 149 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nvkm_clk_read 177 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 215 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c if (core < nvkm_clk_read(&clk->base, nv_clk_src_hclkm4)) nvkm_clk_read 216 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); nvkm_clk_read 242 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) { nvkm_clk_read 56 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); nvkm_clk_read 103 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); nvkm_clk_read 104 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 145 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal); nvkm_clk_read 152 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_dom6); nvkm_clk_read 206 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000); nvkm_clk_read 208 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; nvkm_clk_read 210 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2; nvkm_clk_read 213 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 216 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); nvkm_clk_read 223 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nvkm_clk_read 224 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6); nvkm_clk_read 234 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P; nvkm_clk_read 235 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nvkm_clk_read 246 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nvkm_clk_read 249 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; nvkm_clk_read 267 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nvkm_clk_read 268 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nvkm_clk_read 276 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nvkm_clk_read 282 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nvkm_clk_read 286 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P; nvkm_clk_read 288 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P; nvkm_clk_read 306 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nvkm_clk_read 308 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); nvkm_clk_read 310 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P; nvkm_clk_read 405 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2); nvkm_clk_read 426 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) { nvkm_clk_read 429 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) { nvkm_clk_read 432 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; nvkm_clk_read 189 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c ref = nvkm_clk_read(clk, nv_clk_src_sppll0); nvkm_clk_read 191 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c ref = nvkm_clk_read(clk, nv_clk_src_sppll1); nvkm_clk_read 1122 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_clk_read(clk, nv_clk_src_mem), nvkm_clk_read 187 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c clk_current = nvkm_clk_read(clk, nv_clk_src_mem);