nvif_rd32 204 drivers/gpu/drm/nouveau/dispnv04/arb.c uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); nvif_rd32 224 drivers/gpu/drm/nouveau/dispnv04/arb.c sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; nvif_rd32 225 drivers/gpu/drm/nouveau/dispnv04/arb.c sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; nvif_rd32 83 drivers/gpu/drm/nouveau/dispnv04/dac.c if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) nvif_rd32 89 drivers/gpu/drm/nouveau/dispnv04/dac.c if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) nvif_rd32 95 drivers/gpu/drm/nouveau/dispnv04/dac.c if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) nvif_rd32 263 drivers/gpu/drm/nouveau/dispnv04/dac.c saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2); nvif_rd32 267 drivers/gpu/drm/nouveau/dispnv04/dac.c saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4); nvif_rd32 339 drivers/gpu/drm/nouveau/dispnv04/dfp.c if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) nvif_rd32 177 drivers/gpu/drm/nouveau/dispnv04/hw.c pll1 = nvif_rd32(device, reg1); nvif_rd32 179 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = nvif_rd32(device, reg1 + 4); nvif_rd32 183 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = nvif_rd32(device, reg2); nvif_rd32 748 drivers/gpu/drm/nouveau/dispnv04/hw.c if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) nvif_rd32 752 drivers/gpu/drm/nouveau/dispnv04/hw.c if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) nvif_rd32 66 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd32(device, reg); nvif_rd32 86 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd32(device, reg); nvif_rd32 265 drivers/gpu/drm/nouveau/dispnv04/hw.h return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28)); nvif_rd32 430 drivers/gpu/drm/nouveau/dispnv04/overlay.c nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); nvif_rd32 140 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h return nvif_rd32(&device->object, reg); nvif_rd32 211 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) nvif_rd32 222 drivers/gpu/drm/nouveau/dispnv50/disp.c u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; nvif_rd32 231 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!nvif_rd32(&dmac->base.user, 0x0004)) nvif_rd32 2366 drivers/gpu/drm/nouveau/dispnv50/disp.c crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; nvif_rd32 2369 drivers/gpu/drm/nouveau/dispnv50/disp.c crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; nvif_rd32 66 drivers/gpu/drm/nouveau/include/nvif/object.h u32 _addr = (b), _data = nvif_rd32(__object, _addr); \ nvif_rd32 71 drivers/gpu/drm/nouveau/nouveau_backlight.c int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & nvif_rd32 84 drivers/gpu/drm/nouveau/nouveau_backlight.c int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); nvif_rd32 106 drivers/gpu/drm/nouveau/nouveau_backlight.c if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) nvif_rd32 125 drivers/gpu/drm/nouveau/nouveau_backlight.c val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); nvif_rd32 160 drivers/gpu/drm/nouveau/nouveau_backlight.c div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); nvif_rd32 161 drivers/gpu/drm/nouveau/nouveau_backlight.c val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); nvif_rd32 178 drivers/gpu/drm/nouveau/nouveau_backlight.c div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); nvif_rd32 205 drivers/gpu/drm/nouveau/nouveau_backlight.c if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1))) nvif_rd32 239 drivers/gpu/drm/nouveau/nouveau_bios.c sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; nvif_rd32 335 drivers/gpu/drm/nouveau/nouveau_bios.c return nvif_rd32(device, 0x001800) & 0x0000000f; nvif_rd32 338 drivers/gpu/drm/nouveau/nouveau_bios.c return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; nvif_rd32 340 drivers/gpu/drm/nouveau/nouveau_bios.c return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; nvif_rd32 670 drivers/gpu/drm/nouveau/nouveau_bios.c sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; nvif_rd32 1952 drivers/gpu/drm/nouveau/nouveau_bios.c nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); nvif_rd32 61 drivers/gpu/drm/nouveau/nouveau_debugfs.c nvif_rd32(&drm->client.device.object, 0x101000)); nvif_rd32 58 drivers/gpu/drm/nouveau/nouveau_dma.c val = nvif_rd32(&chan->user, chan->user_get); nvif_rd32 60 drivers/gpu/drm/nouveau/nouveau_dma.c val |= (uint64_t)nvif_rd32(&chan->user, chan->user_get_hi) << 32; nvif_rd32 114 drivers/gpu/drm/nouveau/nouveau_dma.c uint32_t get = nvif_rd32(&chan->user, 0x88); nvif_rd32 44 drivers/gpu/drm/nouveau/nouveau_led.c div = nvif_rd32(device, 0x61c880) & 0x00ffffff; nvif_rd32 45 drivers/gpu/drm/nouveau/nouveau_led.c duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; nvif_rd32 440 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 instlo = nvif_rd32(memory, offset + 0x00); nvif_rd32 441 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 insthi = nvif_rd32(memory, offset + 0x04); nvif_rd32 442 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 addrlo = nvif_rd32(memory, offset + 0x08); nvif_rd32 443 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 addrhi = nvif_rd32(memory, offset + 0x0c); nvif_rd32 444 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 timelo = nvif_rd32(memory, offset + 0x10); nvif_rd32 445 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 timehi = nvif_rd32(memory, offset + 0x14); nvif_rd32 446 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 engine = nvif_rd32(memory, offset + 0x18); nvif_rd32 447 drivers/gpu/drm/nouveau/nouveau_svm.c const u32 info = nvif_rd32(memory, offset + 0x1c); nvif_rd32 551 drivers/gpu/drm/nouveau/nouveau_svm.c buffer->put = nvif_rd32(device, buffer->putaddr); nvif_rd32 552 drivers/gpu/drm/nouveau/nouveau_svm.c buffer->get = nvif_rd32(device, buffer->getaddr); nvif_rd32 753 drivers/gpu/drm/nouveau/nouveau_svm.c buffer->get = nvif_rd32(device, buffer->getaddr); nvif_rd32 754 drivers/gpu/drm/nouveau/nouveau_svm.c buffer->put = nvif_rd32(device, buffer->putaddr); nvif_rd32 53 drivers/gpu/drm/nouveau/nv10_fence.c return nvif_rd32(&chan->user, 0x0048);