nv50_clk           32 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_div(struct nv50_clk *clk)
nv50_clk           52 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_pll_src(struct nv50_clk *clk, u32 base)
nv50_clk          125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_pll_ref(struct nv50_clk *clk, u32 base)
nv50_clk          158 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_pll(struct nv50_clk *clk, u32 base)
nv50_clk          194 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	struct nv50_clk *clk = nv50_clk(base);
nv50_clk          325 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
nv50_clk          370 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	struct nv50_clk *clk = nv50_clk(base);
nv50_clk          497 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	struct nv50_clk *clk = nv50_clk(base);
nv50_clk          504 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	struct nv50_clk *clk = nv50_clk(base);
nv50_clk          512 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	struct nv50_clk *clk;
nv50_clk          542 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nv50_clk = {
nv50_clk          560 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	return nv50_clk_new_(&nv50_clk, device, index, false, pclk);
nv50_clk            4 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h #define nv50_clk(p) container_of((p), struct nv50_clk, base)