nv40_clk 24 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c #define nv40_clk(p) container_of((p), struct nv40_clk, base) nv40_clk 40 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c read_pll_1(struct nv40_clk *clk, u32 reg) nv40_clk 56 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c read_pll_2(struct nv40_clk *clk, u32 reg) nv40_clk 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c read_clk(struct nv40_clk *clk, u32 src) nv40_clk 99 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk = nv40_clk(base); nv40_clk 124 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, nv40_clk 148 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk = nv40_clk(base); nv40_clk 188 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk = nv40_clk(base); nv40_clk 205 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nv40_clk = { nv40_clk 223 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk; nv40_clk 231 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base);