nv10_gr 389 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define nv10_gr(p) container_of((p), struct nv10_gr, base) nv10_gr 401 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr; nv10_gr 547 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_channel(struct nv10_gr *gr) nv10_gr 562 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 581 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 632 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 786 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) nv10_gr 799 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) nv10_gr 814 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 885 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 912 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_context_switch(struct nv10_gr *gr) nv10_gr 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 974 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; nv10_gr 1005 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); nv10_gr 1051 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); nv10_gr 1083 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); nv10_gr 1138 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); nv10_gr 1178 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr; nv10_gr 1189 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr = { nv10_gr 1220 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c return nv10_gr_new_(&nv10_gr, device, index, pgr);