nv04_display       62 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display       77 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display      119 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
nv04_display      236 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display      461 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display      462 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
nv04_display      541 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
nv04_display      607 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_display *disp = nv04_display(crtc->dev);
nv04_display      653 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
nv04_display      663 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
nv04_display      665 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
nv04_display      685 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
nv04_display      690 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
nv04_display      725 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
nv04_display      743 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_display *disp = nv04_display(crtc->dev);
nv04_display      770 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
nv04_display      781 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
nv04_display      787 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_display *disp = nv04_display(crtc->dev);
nv04_display      824 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display     1152 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_display *dispnv04 = nv04_display(dev);
nv04_display       42 drivers/gpu/drm/nouveau/dispnv04/cursor.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display      431 drivers/gpu/drm/nouveau/dispnv04/dac.c 		uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1];
nv04_display      456 drivers/gpu/drm/nouveau/dispnv04/dac.c 		(nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
nv04_display       95 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
nv04_display      122 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
nv04_display      137 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
nv04_display      206 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
nv04_display      236 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
nv04_display      237 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
nv04_display      250 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
nv04_display      287 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display      288 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
nv04_display      463 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
nv04_display      554 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
nv04_display      555 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
nv04_display      557 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
nv04_display      603 drivers/gpu/drm/nouveau/dispnv04/dfp.c 					(&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
nv04_display       39 drivers/gpu/drm/nouveau/dispnv04/disp.c 	struct nv04_display *disp = nv04_display(dev);
nv04_display       77 drivers/gpu/drm/nouveau/dispnv04/disp.c 	struct nv04_display *disp = nv04_display(dev);
nv04_display      165 drivers/gpu/drm/nouveau/dispnv04/disp.c 	struct nv04_display *disp = nv04_display(dev);
nv04_display      197 drivers/gpu/drm/nouveau/dispnv04/disp.c 	struct nv04_display *disp;
nv04_display       88 drivers/gpu/drm/nouveau/dispnv04/disp.h static inline struct nv04_display *
nv04_display      298 drivers/gpu/drm/nouveau/dispnv04/hw.c 			nv04_display(dev)->saved_vga_font[plane][i] =
nv04_display      301 drivers/gpu/drm/nouveau/dispnv04/hw.c 			iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
nv04_display      376 drivers/gpu/drm/nouveau/dispnv04/hw.h 		&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
nv04_display      547 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
nv04_display       79 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
nv04_display      107 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
nv04_display      146 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_display      403 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
nv04_display      464 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];