nv04_crtc_reg      52 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
nv04_crtc_reg      62 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg      77 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg     120 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
nv04_crtc_reg     236 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg     461 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg     462 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg     664 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
nv04_crtc_reg     666 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
nv04_crtc_reg     824 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg      31 drivers/gpu/drm/nouveau/dispnv04/cursor.c crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
nv04_crtc_reg      42 drivers/gpu/drm/nouveau/dispnv04/cursor.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg      95 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
nv04_crtc_reg     250 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
nv04_crtc_reg     287 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg     288 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg      74 drivers/gpu/drm/nouveau/dispnv04/disp.h 	struct nv04_crtc_reg crtc_reg[2];
nv04_crtc_reg     378 drivers/gpu/drm/nouveau/dispnv04/hw.c 	     struct nv04_crtc_reg *crtcstate, int index)
nv04_crtc_reg     385 drivers/gpu/drm/nouveau/dispnv04/hw.c 	     struct nv04_crtc_reg *crtcstate, int index)
nv04_crtc_reg     395 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
nv04_crtc_reg     471 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
nv04_crtc_reg     541 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
nv04_crtc_reg     565 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
nv04_crtc_reg     592 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
nv04_crtc_reg     668 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
nv04_crtc_reg     547 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
nv04_crtc_reg     107 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
nv04_crtc_reg     146 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nv04_crtc_reg     464 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];