number_of_states_plus_one 211 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 230 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 251 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 298 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 434 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 506 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 519 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 567 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 579 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 589 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 948 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = 0; i <= number_of_states_plus_one; i++) { number_of_states_plus_one 966 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = number_of_states_plus_one; i >= 0; i--) { number_of_states_plus_one 988 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = number_of_states_plus_one; i >= 0; i--) { number_of_states_plus_one 989 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((i == number_of_states_plus_one || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) { number_of_states_plus_one 993 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (i = number_of_states_plus_one; i >= 0; i--) { number_of_states_plus_one 994 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((i == number_of_states_plus_one || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) { number_of_states_plus_one 998 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) { number_of_states_plus_one 1094 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c if (v->voltage_level != number_of_states_plus_one && !fast_validate) { number_of_states_plus_one 1259 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c } else if (v->voltage_level == number_of_states_plus_one) { number_of_states_plus_one 103 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float voltage[number_of_states_plus_one + 1]; number_of_states_plus_one 104 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float max_dispclk[number_of_states_plus_one + 1]; number_of_states_plus_one 105 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float max_dppclk[number_of_states_plus_one + 1]; number_of_states_plus_one 106 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float dcfclk_per_state[number_of_states_plus_one + 1]; number_of_states_plus_one 107 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float phyclk_per_state[number_of_states_plus_one + 1]; number_of_states_plus_one 108 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1]; number_of_states_plus_one 234 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 235 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 236 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 237 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 238 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 239 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 240 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 241 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 242 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 243 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 244 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; number_of_states_plus_one 245 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 246 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 247 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 248 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 249 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float required_dispclk[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 250 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 251 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 252 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 253 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 254 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 255 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 256 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; number_of_states_plus_one 257 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float return_bw_per_state[number_of_states_plus_one + 1]; number_of_states_plus_one 258 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs dio_support[number_of_states_plus_one + 1]; number_of_states_plus_one 259 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1]; number_of_states_plus_one 260 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs rob_support[number_of_states_plus_one + 1]; number_of_states_plus_one 261 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1];