CPL_RX_PHYS_DSGL_PCIRLXORDER_V  398 drivers/crypto/chelsio/chcr_algo.c 		htonl(CPL_RX_PHYS_DSGL_PCIRLXORDER_V(0) |
CPL_RX_PHYS_DSGL_PCIRLXORDER_V 2111 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F  CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)