nps_mtm_reg_addr   28 arch/arc/plat-eznps/include/plat/mtm.h #define MTM_CFG(cpu)			nps_mtm_reg_addr(cpu, 0x81)
nps_mtm_reg_addr   29 arch/arc/plat-eznps/include/plat/mtm.h #define MTM_THR_INIT(cpu)		nps_mtm_reg_addr(cpu, 0x92)
nps_mtm_reg_addr   30 arch/arc/plat-eznps/include/plat/mtm.h #define MTM_THR_INIT_STS(cpu)		nps_mtm_reg_addr(cpu, 0x93)
nps_mtm_reg_addr   95 arch/arc/plat-eznps/smp.c 	iowrite32be(cpu_cfg.value, nps_mtm_reg_addr(cpu, NPS_MTM_CPU_CFG));