nlm_write_reg 137 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(base, reg, val); nlm_write_reg 179 arch/mips/include/asm/netlogic/xlp-hal/bridge.h #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 201 arch/mips/include/asm/netlogic/xlp-hal/iomap.h #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 100 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 195 arch/mips/include/asm/netlogic/xlp-hal/sys.h #define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 95 arch/mips/include/asm/netlogic/xlp-hal/uart.h #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 228 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); nlm_write_reg 237 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); nlm_write_reg 247 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IPI, nlm_write_reg 254 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_INT_ACK, 1u << irt); nlm_write_reg 260 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); nlm_write_reg 262 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), nlm_write_reg 297 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); nlm_write_reg 298 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); nlm_write_reg 303 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_CTRL, pic_ctrl); nlm_write_reg 62 arch/mips/netlogic/common/earlycons.c nlm_write_reg(uartbase, UART_TX, c); nlm_write_reg 144 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 88 arch/mips/netlogic/xlp/ahci-init.c #define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 85 arch/mips/netlogic/xlp/usb-init-xlp2.c #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 64 arch/mips/netlogic/xlp/usb-init.c #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) nlm_write_reg 98 arch/mips/netlogic/xlr/platform-flash.c nlm_write_reg(nand_priv.flash_mmio, nlm_write_reg 101 arch/mips/netlogic/xlr/platform-flash.c nlm_write_reg(nand_priv.flash_mmio, nlm_write_reg 196 arch/mips/netlogic/xlr/platform-flash.c nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs), nlm_write_reg 198 arch/mips/netlogic/xlr/platform-flash.c nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs), nlm_write_reg 200 arch/mips/netlogic/xlr/platform-flash.c nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs), nlm_write_reg 57 arch/mips/netlogic/xlr/platform.c nlm_write_reg(uartbase, offset, value); nlm_write_reg 160 arch/mips/netlogic/xlr/platform.c nlm_write_reg(usb_mmio, 49, 0x10000000); nlm_write_reg 162 arch/mips/netlogic/xlr/platform.c nlm_write_reg(usb_mmio, 50, 0x1f000000); nlm_write_reg 165 arch/mips/netlogic/xlr/platform.c nlm_write_reg(usb_mmio, 1, 0x07000500); nlm_write_reg 170 arch/mips/netlogic/xlr/platform.c nlm_write_reg(usb_mmio, 0, 0x01000000); nlm_write_reg 176 arch/mips/netlogic/xlr/platform.c nlm_write_reg(usb_mmio, 0, 0x02000000); nlm_write_reg 69 arch/mips/netlogic/xlr/setup.c nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1); nlm_write_reg 142 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN, nlm_write_reg 145 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); nlm_write_reg 159 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN, nlm_write_reg 162 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); nlm_write_reg 177 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec); nlm_write_reg 179 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec); nlm_write_reg 224 arch/mips/pci/msi-xlp.c nlm_write_reg(md->lnkbase, status_reg, 1u << bit); nlm_write_reg 256 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); nlm_write_reg 262 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_INT_EN0, val); nlm_write_reg 269 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, 0x1, val); nlm_write_reg 279 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32); nlm_write_reg 280 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff); nlm_write_reg 286 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val); nlm_write_reg 353 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, 0x2C, val); nlm_write_reg 360 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); nlm_write_reg 366 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_INT_EN0, val); nlm_write_reg 373 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, 0x1, val); nlm_write_reg 384 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE, nlm_write_reg 386 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT, nlm_write_reg 390 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, nlm_write_reg 392 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT, nlm_write_reg 283 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); nlm_write_reg 286 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); nlm_write_reg 289 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); nlm_write_reg 292 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); nlm_write_reg 304 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); nlm_write_reg 307 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); nlm_write_reg 310 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); nlm_write_reg 313 arch/mips/pci/pci-xlr.c nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);