nlm_read_reg      131 arch/mips/include/asm/netlogic/haldefs.h 	return nlm_read_reg(base, reg);
nlm_read_reg      178 arch/mips/include/asm/netlogic/xlp-hal/bridge.h #define nlm_read_bridge_reg(b, r)	nlm_read_reg(b, r)
nlm_read_reg      200 arch/mips/include/asm/netlogic/xlp-hal/iomap.h #define nlm_read_pci_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg       99 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h #define nlm_read_pcie_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg      194 arch/mips/include/asm/netlogic/xlp-hal/sys.h #define nlm_read_sys_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg       94 arch/mips/include/asm/netlogic/xlp-hal/uart.h #define nlm_read_uart_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg      227 arch/mips/include/asm/netlogic/xlr/pic.h 	reg = nlm_read_reg(base, PIC_IRT_1(irt));
nlm_read_reg      236 arch/mips/include/asm/netlogic/xlr/pic.h 	reg = nlm_read_reg(base, PIC_IRT_1(irt));
nlm_read_reg      271 arch/mips/include/asm/netlogic/xlr/pic.h 	up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
nlm_read_reg      272 arch/mips/include/asm/netlogic/xlr/pic.h 	low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
nlm_read_reg      273 arch/mips/include/asm/netlogic/xlr/pic.h 	up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
nlm_read_reg      276 arch/mips/include/asm/netlogic/xlr/pic.h 		low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
nlm_read_reg      284 arch/mips/include/asm/netlogic/xlr/pic.h 	return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
nlm_read_reg      291 arch/mips/include/asm/netlogic/xlr/pic.h 	uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
nlm_read_reg       60 arch/mips/netlogic/common/earlycons.c 	while ((nlm_read_reg(uartbase, UART_LSR) & UART_LSR_THRE) == 0)
nlm_read_reg      143 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define nlm_read_sata_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg       87 arch/mips/netlogic/xlp/ahci-init.c #define nlm_read_sata_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg      188 arch/mips/netlogic/xlp/nlm_hal.c 		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
nlm_read_reg       84 arch/mips/netlogic/xlp/usb-init-xlp2.c #define nlm_read_usb_reg(b, r)		nlm_read_reg(b, r)
nlm_read_reg       63 arch/mips/netlogic/xlp/usb-init.c #define nlm_read_usb_reg(b, r)			nlm_read_reg(b, r)
nlm_read_reg      126 arch/mips/netlogic/xlp/wakeup.c 				if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
nlm_read_reg      137 arch/mips/netlogic/xlp/wakeup.c 			fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
nlm_read_reg      147 arch/mips/netlogic/xlr/platform-flash.c 	base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
nlm_read_reg      148 arch/mips/netlogic/xlr/platform-flash.c 	mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
nlm_read_reg      161 arch/mips/netlogic/xlr/platform-flash.c 	flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
nlm_read_reg      168 arch/mips/netlogic/xlr/platform-flash.c 	gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
nlm_read_reg       33 arch/mips/netlogic/xlr/platform.c 	value = nlm_read_reg(uartbase, offset);
nlm_read_reg      167 arch/mips/netlogic/xlr/platform.c 	val = nlm_read_reg(gpio_mmio, 21);
nlm_read_reg      253 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
nlm_read_reg      259 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
nlm_read_reg      266 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, 0x1);	/* CMD */
nlm_read_reg      283 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
nlm_read_reg      350 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, 0x2C);
nlm_read_reg      357 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
nlm_read_reg      363 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
nlm_read_reg      370 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, 0x1);	/* CMD */
nlm_read_reg      525 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
nlm_read_reg      528 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
nlm_read_reg      555 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
nlm_read_reg      557 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
nlm_read_reg      273 arch/mips/pci/pci-xlr.c 	nlm_read_reg(pcibase, (0x140 >> 2));