nitrox_write_csr 30 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); nitrox_write_csr 31 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); nitrox_write_csr 58 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, emu_wd_int.value); nitrox_write_csr 60 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, emu_ge_int.value); nitrox_write_csr 75 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_in_ctl.value); nitrox_write_csr 89 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_in_cnts.value); nitrox_write_csr 104 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_in_ctl.value); nitrox_write_csr 137 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, cmdq->dma); nitrox_write_csr 143 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_in_rsize.value); nitrox_write_csr 147 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, 0xffffffff); nitrox_write_csr 153 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_in_dbell.value); nitrox_write_csr 171 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); nitrox_write_csr 186 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); nitrox_write_csr 206 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); nitrox_write_csr 229 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, pkt_slc_int.value); nitrox_write_csr 260 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value); nitrox_write_csr 268 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL); nitrox_write_csr 274 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value); nitrox_write_csr 289 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); nitrox_write_csr 290 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); nitrox_write_csr 291 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); nitrox_write_csr 293 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); nitrox_write_csr 294 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); nitrox_write_csr 295 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL)); nitrox_write_csr 320 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, aqmq_en_reg.value); nitrox_write_csr 335 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, cmp_cnt.value); nitrox_write_csr 347 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, aqmq_en_reg.value); nitrox_write_csr 369 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, drbl.value); nitrox_write_csr 375 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, 0ULL); nitrox_write_csr 379 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, cmdq->dma); nitrox_write_csr 385 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, qsize.value); nitrox_write_csr 391 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, cmp_thr.value); nitrox_write_csr 401 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); nitrox_write_csr 402 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); nitrox_write_csr 403 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); nitrox_write_csr 404 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); nitrox_write_csr 405 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL)); nitrox_write_csr 406 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL)); nitrox_write_csr 407 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL)); nitrox_write_csr 408 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL)); nitrox_write_csr 428 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value); nitrox_write_csr 432 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i)); nitrox_write_csr 448 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); nitrox_write_csr 465 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, efl_core_int.value); nitrox_write_csr 468 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 470 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 486 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, bmi_ctl.value); nitrox_write_csr 494 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, bmi_int_ena.value); nitrox_write_csr 506 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, bmo_ctl2.value); nitrox_write_csr 520 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, lbc_ctl.value); nitrox_write_csr 545 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, lbc_int_ena.value); nitrox_write_csr 548 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 550 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 553 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 555 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 565 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value); nitrox_write_csr 659 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, reg_addr, value); nitrox_write_csr 663 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, reg_addr, value); nitrox_write_csr 673 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, reg_addr, value); nitrox_write_csr 677 drivers/crypto/cavium/nitrox/nitrox_hal.c nitrox_write_csr(ndev, reg_addr, value); nitrox_write_csr 47 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, NPS_CORE_INT, value); nitrox_write_csr 65 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 71 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 81 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 89 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 94 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 104 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 115 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, POM_INT, value); nitrox_write_csr 124 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, PEM0_INT, value); nitrox_write_csr 141 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 144 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 156 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 159 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 165 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 168 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 170 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, LBC_INT, lbc_int.value); nitrox_write_csr 183 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, core_int.value); nitrox_write_csr 189 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, offset, value); nitrox_write_csr 199 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, BMI_INT, value); nitrox_write_csr 257 drivers/crypto/cavium/nitrox/nitrox_isr.c nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value); nitrox_write_csr 104 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, block_num); nitrox_write_csr 111 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, data); nitrox_write_csr 163 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, (~0ULL)); nitrox_write_csr 179 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, core_2_eid_val.value); nitrox_write_csr 215 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, aqm_grp_execmask_lo.value); nitrox_write_csr 218 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, aqm_grp_execmask_hi.value); nitrox_write_csr 234 drivers/crypto/cavium/nitrox/nitrox_main.c nitrox_write_csr(ndev, offset, core_2_eid_val.value); nitrox_write_csr 50 drivers/crypto/cavium/nitrox/nitrox_mbx.c nitrox_write_csr(ndev, reg_addr, value); nitrox_write_csr 139 drivers/crypto/cavium/nitrox/nitrox_mbx.c nitrox_write_csr(ndev, reg_addr, BIT_ULL(i)); nitrox_write_csr 162 drivers/crypto/cavium/nitrox/nitrox_mbx.c nitrox_write_csr(ndev, reg_addr, BIT_ULL(i));