CORE_CLK_SRC_DPLL   80 arch/arm/mach-omap2/clkt2xxx_dpllcore.c 	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
CORE_CLK_SRC_DPLL  121 arch/arm/mach-omap2/clkt2xxx_dpllcore.c 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
CORE_CLK_SRC_DPLL  150 arch/arm/mach-omap2/clkt2xxx_dpllcore.c 			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
CORE_CLK_SRC_DPLL  152 arch/arm/mach-omap2/clkt2xxx_dpllcore.c 			done_rate = CORE_CLK_SRC_DPLL;
CORE_CLK_SRC_DPLL  126 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
CORE_CLK_SRC_DPLL  139 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c 			done_rate = CORE_CLK_SRC_DPLL;
CORE_CLK_SRC_DPLL   88 arch/arm/mach-omap2/sdrc2xxx.c 	if (level == CORE_CLK_SRC_DPLL)