mxc_iomux_alloc_pin 113 arch/arm/mach-imx/iomux-imx31.c ret = mxc_iomux_alloc_pin(*p, label); mxc_iomux_alloc_pin 102 arch/arm/mach-imx/iomux-mx3.h int mxc_iomux_alloc_pin(unsigned int pin, const char *label); mxc_iomux_alloc_pin 217 arch/arm/mach-imx/mach-mx31ads.c mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); mxc_iomux_alloc_pin 188 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), mxc_iomux_alloc_pin 265 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); mxc_iomux_alloc_pin 268 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK"); mxc_iomux_alloc_pin 269 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX"); mxc_iomux_alloc_pin 270 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX"); mxc_iomux_alloc_pin 271 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY"); mxc_iomux_alloc_pin 272 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0"); mxc_iomux_alloc_pin 273 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1"); mxc_iomux_alloc_pin 274 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2"); mxc_iomux_alloc_pin 276 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK"); mxc_iomux_alloc_pin 277 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX"); mxc_iomux_alloc_pin 278 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX"); mxc_iomux_alloc_pin 279 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY"); mxc_iomux_alloc_pin 280 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0"); mxc_iomux_alloc_pin 281 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); mxc_iomux_alloc_pin 282 arch/arm/mach-imx/mach-mx31lilly.c mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); mxc_iomux_alloc_pin 173 arch/arm/mach-imx/mach-mx31lite.c mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),