mvreg_write 760 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), mvreg_write 766 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), mvreg_write 792 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); mvreg_write 812 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); mvreg_write 836 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); mvreg_write 852 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); mvreg_write 870 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); mvreg_write 909 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); mvreg_write 920 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); mvreg_write 931 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); mvreg_write 944 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); mvreg_write 957 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); mvreg_write 976 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); mvreg_write 1002 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_BASE(i), 0); mvreg_write 1003 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); mvreg_write 1006 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); mvreg_write 1008 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | mvreg_write 1011 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); mvreg_write 1015 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); mvreg_write 1018 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); mvreg_write 1142 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); mvreg_write 1159 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_CMD, q_map); mvreg_write 1169 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CMD, q_map); mvreg_write 1183 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CMD, mvreg_write 1206 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_CMD, mvreg_write 1251 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); mvreg_write 1262 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); mvreg_write 1283 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); mvreg_write 1300 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); mvreg_write 1320 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); mvreg_write 1330 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_NEW_MASK, mvreg_write 1343 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); mvreg_write 1344 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); mvreg_write 1345 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); mvreg_write 1355 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); mvreg_write 1356 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); mvreg_write 1357 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); mvreg_write 1381 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_ENABLE, 0); mvreg_write 1384 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); mvreg_write 1416 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); mvreg_write 1420 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); mvreg_write 1421 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); mvreg_write 1424 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); mvreg_write 1426 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); mvreg_write 1427 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); mvreg_write 1430 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); mvreg_write 1431 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); mvreg_write 1440 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_ACC_MODE, val); mvreg_write 1443 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); mvreg_write 1447 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG, val); mvreg_write 1450 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); mvreg_write 1451 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); mvreg_write 1466 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_SDMA_CONFIG, val); mvreg_write 1473 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_UNIT_CONTROL, val); mvreg_write 1480 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_ENABLE, mvreg_write 1502 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TX_MTU, val); mvreg_write 1512 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); mvreg_write 1522 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); mvreg_write 1554 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); mvreg_write 1569 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); mvreg_write 1570 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); mvreg_write 1583 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), mvreg_write 1599 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); mvreg_write 1613 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); mvreg_write 1638 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); mvreg_write 1643 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); mvreg_write 2595 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, mvreg_write 2628 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); mvreg_write 2688 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); mvreg_write 2689 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); mvreg_write 2696 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); mvreg_write 2697 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TYPE_PRIO, val); mvreg_write 2742 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); mvreg_write 2791 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); mvreg_write 2829 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_NEW_MASK, mvreg_write 2881 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); mvreg_write 2882 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); mvreg_write 2887 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); mvreg_write 2888 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); mvreg_write 2914 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); mvreg_write 2915 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); mvreg_write 3042 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); mvreg_write 3043 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); mvreg_write 3046 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); mvreg_write 3047 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); mvreg_write 3096 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); mvreg_write 3097 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); mvreg_write 3100 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); mvreg_write 3101 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); mvreg_write 3209 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_MISC_MASK, mvreg_write 3465 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, mvreg_write 3467 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, mvreg_write 3552 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, mvreg_write 3575 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); mvreg_write 3577 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); mvreg_write 3579 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); mvreg_write 3581 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); mvreg_write 3583 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); mvreg_write 3601 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); mvreg_write 3617 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); mvreg_write 3636 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); mvreg_write 3716 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); mvreg_write 3778 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_MISC_MASK, mvreg_write 3819 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_INTR_MISC_MASK, mvreg_write 4206 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG, val); mvreg_write 4325 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); mvreg_write 4427 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_BASE(i), 0); mvreg_write 4428 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); mvreg_write 4431 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); mvreg_write 4441 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_BASE(i), mvreg_write 4446 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_SIZE(i), mvreg_write 4457 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); mvreg_write 4462 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); mvreg_write 4463 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); mvreg_write 4470 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); mvreg_write 4473 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); mvreg_write 4476 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);