mvpp2_write      1199 drivers/net/ethernet/marvell/mvpp2/mvpp2.h void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);
mvpp2_write       327 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);
mvpp2_write       336 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, index);
mvpp2_write       346 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
mvpp2_write       347 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
mvpp2_write       348 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
mvpp2_write       349 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
mvpp2_write       354 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);
mvpp2_write       365 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
mvpp2_write       378 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
mvpp2_write       379 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
mvpp2_write       499 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2->index);
mvpp2_write       506 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_INV, val);
mvpp2_write       508 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_ACT, c2->act);
mvpp2_write       510 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR0, c2->attr[0]);
mvpp2_write       511 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR1, c2->attr[1]);
mvpp2_write       512 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR2, c2->attr[2]);
mvpp2_write       513 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR3, c2->attr[3]);
mvpp2_write       515 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]);
mvpp2_write       516 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]);
mvpp2_write       517 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]);
mvpp2_write       518 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]);
mvpp2_write       520 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]);
mvpp2_write       527 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, index);
mvpp2_write       910 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
mvpp2_write       941 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_CTRL,
mvpp2_write       955 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
mvpp2_write       979 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2_index);
mvpp2_write      1066 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
mvpp2_write      1069 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
mvpp2_write      1074 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
mvpp2_write      1473 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 		mvpp2_write(priv, MVPP22_RSS_INDEX, sel);
mvpp2_write      1475 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 		mvpp2_write(priv, MVPP22_RSS_TABLE_ENTRY,
mvpp2_write      1504 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_TABLE(ctx));
mvpp2_write      1505 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_RSS_WIDTH, 8);
mvpp2_write      1507 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_QUEUE(ctx));
mvpp2_write      1508 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	mvpp2_write(priv, MVPP22_RXQ2RSS_TABLE, MVPP22_RSS_TABLE_POINTER(ctx));
mvpp2_write       380 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
mvpp2_write       382 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
mvpp2_write       386 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
mvpp2_write       405 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
mvpp2_write       509 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
mvpp2_write       556 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
mvpp2_write       558 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
mvpp2_write       606 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
mvpp2_write       627 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
mvpp2_write      1018 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
mvpp2_write      1029 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
mvpp2_write      1037 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
mvpp2_write      1045 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
mvpp2_write      1415 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);
mvpp2_write      1709 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
mvpp2_write      1711 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
mvpp2_write      1714 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
mvpp2_write      1718 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv,
mvpp2_write      1724 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
mvpp2_write      1730 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
mvpp2_write      1732 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
mvpp2_write      1735 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
mvpp2_write      1745 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
mvpp2_write      1762 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
mvpp2_write      1775 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
mvpp2_write      1797 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
mvpp2_write      1798 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
mvpp2_write      1811 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
mvpp2_write      1815 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
mvpp2_write      1860 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
mvpp2_write      1890 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
mvpp2_write      2108 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
mvpp2_write      2114 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
mvpp2_write      2123 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
mvpp2_write      2135 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 			mvpp2_write(port->priv,
mvpp2_write      2210 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
mvpp2_write      2226 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
mvpp2_write      2343 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
mvpp2_write      2344 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
mvpp2_write      2370 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
mvpp2_write      2444 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
mvpp2_write      2502 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
mvpp2_write      2508 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
mvpp2_write      2511 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
mvpp2_write      2575 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
mvpp2_write      2645 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
mvpp2_write      2656 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
mvpp2_write      3357 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
mvpp2_write      4517 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
mvpp2_write      4531 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
mvpp2_write      4535 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
mvpp2_write      5468 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
mvpp2_write      5469 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
mvpp2_write      5472 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 			mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
mvpp2_write      5480 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_WIN_BASE(i),
mvpp2_write      5484 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_WIN_SIZE(i),
mvpp2_write      5490 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
mvpp2_write      5499 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
mvpp2_write      5501 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
mvpp2_write      5505 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
mvpp2_write      5507 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
mvpp2_write      5521 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
mvpp2_write      5523 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
mvpp2_write      5526 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
mvpp2_write      5528 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
mvpp2_write      5532 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
mvpp2_write      5534 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
mvpp2_write      5538 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
mvpp2_write      5540 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
mvpp2_write      5559 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
mvpp2_write      5560 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
mvpp2_write      5568 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
mvpp2_write      5583 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
mvpp2_write      5584 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
mvpp2_write      5587 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
mvpp2_write      5588 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
mvpp2_write      5589 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
mvpp2_write      5590 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
mvpp2_write      5593 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
mvpp2_write      5594 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
mvpp2_write      5600 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
mvpp2_write      5601 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
mvpp2_write      5608 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
mvpp2_write      5615 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
mvpp2_write      5672 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
mvpp2_write        33 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
mvpp2_write        35 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]);
mvpp2_write        38 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
mvpp2_write        40 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]);
mvpp2_write        58 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
mvpp2_write        69 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
mvpp2_write        80 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
mvpp2_write        81 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
mvpp2_write      1077 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
mvpp2_write      1083 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
mvpp2_write      1091 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
mvpp2_write      2101 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
mvpp2_write      2105 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
mvpp2_write      2107 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
mvpp2_write      2109 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
mvpp2_write      2111 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
mvpp2_write      2491 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_write(priv, MVPP2_PRS_TCAM_HIT_IDX_REG, index);