mv_chan_to_devp   129 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
mv_chan_to_devp   158 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
mv_chan_to_devp   181 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
mv_chan_to_devp   219 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
mv_chan_to_devp   238 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
mv_chan_to_devp   272 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
mv_chan_to_devp   273 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
mv_chan_to_devp   390 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan),
mv_chan_to_devp   407 drivers/dma/mv_xor.c 		dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
mv_chan_to_devp   448 drivers/dma/mv_xor.c 			dev_info(mv_chan_to_devp(mv_chan),
mv_chan_to_devp   470 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan),
mv_chan_to_devp   567 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan),
mv_chan_to_devp   592 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan),
mv_chan_to_devp   659 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
mv_chan_to_devp   664 drivers/dma/mv_xor.c 		dev_err(mv_chan_to_devp(mv_chan),
mv_chan_to_devp   697 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "config       0x%08x\n", val);
mv_chan_to_devp   700 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "activation   0x%08x\n", val);
mv_chan_to_devp   703 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "intr cause   0x%08x\n", val);
mv_chan_to_devp   706 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "intr mask    0x%08x\n", val);
mv_chan_to_devp   709 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "error cause  0x%08x\n", val);
mv_chan_to_devp   712 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "error addr   0x%08x\n", val);
mv_chan_to_devp   719 drivers/dma/mv_xor.c 		dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
mv_chan_to_devp   723 drivers/dma/mv_xor.c 	dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
mv_chan_to_devp   735 drivers/dma/mv_xor.c 	dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);