mul_u32_u32        72 arch/x86/include/asm/div64.h #define mul_u32_u32 mul_u32_u32
mul_u32_u32        62 drivers/gpu/drm/drm_rect.c 	tmp = mul_u32_u32(src, dst - clip);
mul_u32_u32       129 drivers/gpu/drm/i915/display/intel_color.c 		result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
mul_u32_u32       580 drivers/gpu/drm/i915/display/intel_display.c 	clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
mul_u32_u32       965 drivers/gpu/drm/i915/display/intel_display.c 			m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
mul_u32_u32      2405 drivers/gpu/drm/i915/display/intel_display.c 	if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
mul_u32_u32      2783 drivers/gpu/drm/i915/display/intel_display.c 	if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
mul_u32_u32      2785 drivers/gpu/drm/i915/display/intel_display.c 			      mul_u32_u32(max_size, tile_size), obj->base.size);
mul_u32_u32      7399 drivers/gpu/drm/i915/display/intel_display.c 		pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
mul_u32_u32      7519 drivers/gpu/drm/i915/display/intel_display.c 	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
mul_u32_u32      11389 drivers/gpu/drm/i915/display/intel_display.c 	return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
mul_u32_u32       499 drivers/gpu/drm/i915/display/intel_dp.c 	return div_u64(mul_u32_u32(mode_clock, 1000000U),
mul_u32_u32      2792 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		tmp = mul_u32_u32(dco_khz, 47 * 32);
mul_u32_u32      2796 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		tmp = mul_u32_u32(dco_khz, 1000);
mul_u32_u32       475 drivers/gpu/drm/i915/display/intel_panel.c 	target_val = mul_u32_u32(source_val - source_min,
mul_u32_u32        79 drivers/gpu/drm/i915/i915_fixed.h 	tmp = mul_u32_u32(val, mul.val);
mul_u32_u32        91 drivers/gpu/drm/i915/i915_fixed.h 	tmp = mul_u32_u32(val.val, mul.val);
mul_u32_u32       122 drivers/gpu/drm/i915/i915_fixed.h 	tmp = mul_u32_u32(val, mul.val);
mul_u32_u32       877 drivers/gpu/drm/i915/i915_irq.c 	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
mul_u32_u32       221 drivers/gpu/drm/i915/i915_pmu.c 	sample->cur += mul_u32_u32(val, mul);
mul_u32_u32       691 drivers/gpu/drm/i915/intel_pm.c 	ret = mul_u32_u32(pixel_rate, cpp * latency);
mul_u32_u32        49 drivers/gpu/drm/i915/selftests/i915_random.h 	return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));
mul_u32_u32       164 include/linux/math64.h #ifndef mul_u32_u32
mul_u32_u32       201 include/linux/math64.h 	ret = mul_u32_u32(al, mul) >> shift;
mul_u32_u32       203 include/linux/math64.h 		ret += mul_u32_u32(ah, mul) << (32 - shift);
mul_u32_u32       227 include/linux/math64.h 	rl.ll = mul_u32_u32(a0.l.low, b0.l.low);
mul_u32_u32       228 include/linux/math64.h 	rm.ll = mul_u32_u32(a0.l.low, b0.l.high);
mul_u32_u32       229 include/linux/math64.h 	rn.ll = mul_u32_u32(a0.l.high, b0.l.low);
mul_u32_u32       230 include/linux/math64.h 	rh.ll = mul_u32_u32(a0.l.high, b0.l.high);
mul_u32_u32       270 include/linux/math64.h 	rl.ll = mul_u32_u32(u.l.low, mul);
mul_u32_u32       271 include/linux/math64.h 	rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high;