mtk_hdmi_phy_mask   49 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
mtk_hdmi_phy_mask  131 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
mtk_hdmi_phy_mask  133 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
mtk_hdmi_phy_mask  135 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
mtk_hdmi_phy_mask  137 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
mtk_hdmi_phy_mask  139 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
mtk_hdmi_phy_mask  141 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
mtk_hdmi_phy_mask  143 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
mtk_hdmi_phy_mask  145 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
mtk_hdmi_phy_mask  147 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
mtk_hdmi_phy_mask  151 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
mtk_hdmi_phy_mask  154 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
mtk_hdmi_phy_mask  156 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
mtk_hdmi_phy_mask  157 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
mtk_hdmi_phy_mask  232 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
mtk_hdmi_phy_mask  235 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
mtk_hdmi_phy_mask  238 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
mtk_hdmi_phy_mask  240 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
mtk_hdmi_phy_mask  243 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
mtk_hdmi_phy_mask  245 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
mtk_hdmi_phy_mask  263 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
mtk_hdmi_phy_mask  272 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
mtk_hdmi_phy_mask  275 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
mtk_hdmi_phy_mask  282 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,