mtk_hdmi_phy_clear_bits 45 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, mtk_hdmi_phy_clear_bits 73 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); mtk_hdmi_phy_clear_bits 93 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); mtk_hdmi_phy_clear_bits 94 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); mtk_hdmi_phy_clear_bits 95 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); mtk_hdmi_phy_clear_bits 96 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); mtk_hdmi_phy_clear_bits 98 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); mtk_hdmi_phy_clear_bits 99 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); mtk_hdmi_phy_clear_bits 100 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); mtk_hdmi_phy_clear_bits 102 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); mtk_hdmi_phy_clear_bits 103 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); mtk_hdmi_phy_clear_bits 104 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); mtk_hdmi_phy_clear_bits 105 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); mtk_hdmi_phy_clear_bits 150 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); mtk_hdmi_phy_clear_bits 153 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); mtk_hdmi_phy_clear_bits 206 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); mtk_hdmi_phy_clear_bits 223 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); mtk_hdmi_phy_clear_bits 224 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); mtk_hdmi_phy_clear_bits 225 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); mtk_hdmi_phy_clear_bits 226 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); mtk_hdmi_phy_clear_bits 228 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); mtk_hdmi_phy_clear_bits 229 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); mtk_hdmi_phy_clear_bits 230 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); mtk_hdmi_phy_clear_bits 232 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); mtk_hdmi_phy_clear_bits 233 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); mtk_hdmi_phy_clear_bits 234 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); mtk_hdmi_phy_clear_bits 235 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); mtk_hdmi_phy_clear_bits 166 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); mtk_hdmi_phy_clear_bits 183 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); mtk_hdmi_phy_clear_bits 184 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); mtk_hdmi_phy_clear_bits 186 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); mtk_hdmi_phy_clear_bits 188 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); mtk_hdmi_phy_clear_bits 189 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); mtk_hdmi_phy_clear_bits 190 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); mtk_hdmi_phy_clear_bits 251 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, mtk_hdmi_phy_clear_bits 320 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,