mtdcr             296 arch/powerpc/boot/4xx.c 	mtdcr(DCRN_MAL0_CFG, MAL_RESET);
mtdcr             312 arch/powerpc/boot/4xx.c 		mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
mtdcr             609 arch/powerpc/boot/4xx.c 	mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
mtdcr              29 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
mtdcr              32 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
mtdcr              33 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_SDRAM0_CFGDATA, data); })
mtdcr             182 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
mtdcr             185 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
mtdcr             186 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
mtdcr             200 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_CPR0_CFGADDR, offset); \
mtdcr             203 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_CPR0_CFGADDR, offset); \
mtdcr             204 arch/powerpc/boot/dcr.h 	mtdcr(DCRN_CPR0_CFGDATA, data); })
mtdcr              30 arch/powerpc/include/asm/dcr-native.h #define dcr_write_native(host, dcr_n, value)	mtdcr(dcr_n + host.base, value)
mtdcr             251 arch/powerpc/platforms/44x/fsp2.c 	mtdcr(DCRN_PLB6_BASE, val);
mtdcr             252 arch/powerpc/platforms/44x/fsp2.c 	mtdcr(DCRN_PLB6_HD, 0xffff0000);
mtdcr             253 arch/powerpc/platforms/44x/fsp2.c 	mtdcr(DCRN_PLB6_SHD, 0xffff0000);
mtdcr             297 arch/powerpc/platforms/44x/fsp2.c 	mtdcr(DCRN_CONF_EIR_RS, 0x80000000);
mtdcr             249 arch/powerpc/platforms/44x/fsp2.h 	mtdcr(DCRN_CMU_ADDR, reg);	\
mtdcr             250 arch/powerpc/platforms/44x/fsp2.h 	mtdcr(DCRN_CMU_DATA, data);	\
mtdcr             255 arch/powerpc/platforms/44x/fsp2.h 	mtdcr(DCRN_CMU_ADDR, reg);	\
mtdcr             261 arch/powerpc/platforms/44x/fsp2.h 	mtdcr(DCRN_L2CDCRAI, reg);	\
mtdcr             262 arch/powerpc/platforms/44x/fsp2.h 	mtdcr(DCRN_L2CDCRDI, data);	\
mtdcr             267 arch/powerpc/platforms/44x/fsp2.h 	mtdcr(DCRN_L2CDCRAI, reg);	\
mtdcr              34 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
mtdcr              35 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
mtdcr              61 arch/powerpc/platforms/4xx/soc.c 		mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
mtdcr              62 arch/powerpc/platforms/4xx/soc.c 		mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
mtdcr             125 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
mtdcr             127 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
mtdcr             129 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
mtdcr             131 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
mtdcr             133 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
mtdcr             140 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
mtdcr             142 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
mtdcr             145 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
mtdcr             150 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
mtdcr             156 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
mtdcr             161 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
mtdcr             177 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
mtdcr              61 arch/powerpc/platforms/4xx/uic.c 		mtdcr(uic->dcrbase + UIC_SR, sr);
mtdcr              64 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_ER, er);
mtdcr              78 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_ER, er);
mtdcr              89 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
mtdcr             104 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_ER, er);
mtdcr             114 arch/powerpc/platforms/4xx/uic.c 		mtdcr(uic->dcrbase + UIC_SR, sr);
mtdcr             155 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_PR, pr);
mtdcr             156 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_TR, tr);
mtdcr             157 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_SR, ~mask);
mtdcr             263 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_ER, 0);
mtdcr             264 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_CR, 0);
mtdcr             265 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_TR, 0);
mtdcr             267 arch/powerpc/platforms/4xx/uic.c 	mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);