mtcr 22 arch/csky/abiv1/inc/abi/entry.h mtcr sp, usp mtcr 27 arch/csky/abiv1/inc/abi/entry.h mtcr sp, ss0 mtcr 32 arch/csky/abiv1/inc/abi/entry.h mtcr r13, ss2 mtcr 86 arch/csky/abiv1/inc/abi/entry.h mtcr a0, epc mtcr 88 arch/csky/abiv1/inc/abi/entry.h mtcr a0, epsr mtcr 92 arch/csky/abiv1/inc/abi/entry.h mtcr a0, ss1 mtcr 158 arch/csky/abiv1/inc/abi/entry.h mtcr r6, psr mtcr 57 arch/csky/abiv2/fpu.c mtcr("cr<1, 2>", regx); mtcr 59 arch/csky/abiv2/fpu.c mtcr("cr<2, 2>", regx); mtcr 222 arch/csky/abiv2/fpu.c mtcr("cr<1, 2>", tmp1); mtcr 223 arch/csky/abiv2/fpu.c mtcr("cr<2, 2>", tmp2); mtcr 17 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<0, 15>", value); mtcr 32 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<6, 15>", value); mtcr 42 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<4, 15>", value); mtcr 52 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<30, 15>", value); mtcr 62 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<31, 15>", value); mtcr 70 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<8, 15>", 0x80000000); mtcr 75 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<8, 15>", 0x40000000); mtcr 84 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<8, 15>", 0x04000000); mtcr 100 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<8, 15>", 0x02000000); mtcr 106 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<28, 15>", pgd | BIT(0)); mtcr 108 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<29, 15>", pgd | BIT(0)); mtcr 72 arch/csky/abiv2/inc/abi/entry.h mtcr a0, epc mtcr 74 arch/csky/abiv2/inc/abi/entry.h mtcr a0, epsr mtcr 77 arch/csky/abiv2/inc/abi/entry.h mtcr a0, usp mtcr 78 arch/csky/abiv2/inc/abi/entry.h mtcr a0, ss0 mtcr 86 arch/csky/abiv2/inc/abi/entry.h mtcr a0, cr14 mtcr 134 arch/csky/abiv2/inc/abi/entry.h mtcr lr, cr14 mtcr 171 arch/csky/abiv2/inc/abi/entry.h mtcr \rx, cr<4, 15> mtcr 175 arch/csky/abiv2/inc/abi/entry.h mtcr \rx, cr<8, 15> mtcr 181 arch/csky/abiv2/inc/abi/entry.h mtcr r6, psr mtcr 188 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr17 mtcr 192 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr<8, 15> /* Set MCIR */ mtcr 201 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr<6, 15> /* Set MPR with 4K page size */ mtcr 206 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr<4, 15> /* Set MEH */ mtcr 211 arch/csky/abiv2/inc/abi/entry.h mtcr r8, cr<2, 15> /* Set MEL0 */ mtcr 214 arch/csky/abiv2/inc/abi/entry.h mtcr r8, cr<3, 15> /* Set MEL1 */ mtcr 217 arch/csky/abiv2/inc/abi/entry.h mtcr r8, cr<8, 15> /* Set MCIR to write TLB */ mtcr 233 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr<30, 15> /* Set MSA0 */ mtcr 236 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr<31, 15> /* Clr MSA1 */ mtcr 241 arch/csky/abiv2/inc/abi/entry.h mtcr r6, cr18 mtcr 13 arch/csky/abiv2/inc/abi/fpu.h static inline void init_fpu(void) { mtcr("cr<1, 2>", 0); } mtcr 37 arch/csky/include/asm/irqflags.h mtcr("psr", flags); mtcr 179 arch/csky/kernel/smp.c mtcr("cr17", 0x22); mtcr 186 arch/csky/kernel/smp.c mtcr("cr<29, 0>", mask); mtcr 211 arch/csky/kernel/smp.c mtcr("cr31", secondary_hint); mtcr 212 arch/csky/kernel/smp.c mtcr("cr18", secondary_ccr); mtcr 214 arch/csky/kernel/smp.c mtcr("vbr", vec_base); mtcr 48 arch/csky/kernel/traps.c mtcr("vbr", vec_base); mtcr 73 arch/csky/kernel/traps.c mtcr("cr<28, 0>", virt_to_phys(vec_base)); mtcr 27 arch/csky/mm/cachev1.c mtcr("cr22", i); mtcr 28 arch/csky/mm/cachev1.c mtcr("cr17", val); mtcr 34 arch/csky/mm/cachev1.c mtcr("cr17", value | CACHE_CLR); mtcr 38 arch/csky/mm/cachev1.c mtcr("cr24", value | CACHE_CLR); mtcr 72 arch/csky/mm/cachev1.c mtcr("cr24", val); mtcr 140 arch/powerpc/include/asm/exception-64e.h mtcr r14; \ mtcr 39 arch/powerpc/include/asm/ftrace.h mtcr r6; \ mtcr 23 drivers/clocksource/timer-mp-csky.c mtcr(PTIM_LVR, delta); mtcr 30 drivers/clocksource/timer-mp-csky.c mtcr(PTIM_CTLR, 0); mtcr 37 drivers/clocksource/timer-mp-csky.c mtcr(PTIM_CTLR, 1); mtcr 44 drivers/clocksource/timer-mp-csky.c mtcr(PTIM_CTLR, 0); mtcr 66 drivers/clocksource/timer-mp-csky.c mtcr(PTIM_TSR, 0); mtcr 69 tools/testing/selftests/powerpc/include/basic_asm.h mtcr r0; \