msr_set_bit 3698 arch/x86/events/intel/core.c msr_set_bit(MSR_IA32_DEBUGCTLMSR, msr_set_bit 335 arch/x86/include/asm/msr.h int msr_set_bit(u32 msr, u8 bit); msr_set_bit 493 arch/x86/kernel/amd_nb.c msr_set_bit(MSR_AMD64_IC_CFG, 3); msr_set_bit 494 arch/x86/kernel/amd_nb.c msr_set_bit(MSR_AMD64_IC_CFG, 14); msr_set_bit 694 arch/x86/kernel/cpu/amd.c msr_set_bit(MSR_AMD64_LS_CFG, 15); msr_set_bit 712 arch/x86/kernel/cpu/amd.c if (msr_set_bit(0xc0011005, 54) > 0) { msr_set_bit 758 arch/x86/kernel/cpu/amd.c msr_set_bit(MSR_K7_HWCR, 6); msr_set_bit 781 arch/x86/kernel/cpu/amd.c msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); msr_set_bit 806 arch/x86/kernel/cpu/amd.c msr_set_bit(MSR_AMD64_DE_CFG, 31); msr_set_bit 960 arch/x86/kernel/cpu/amd.c msr_set_bit(MSR_F10H_DECFG, msr_set_bit 990 arch/x86/kernel/cpu/amd.c msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); msr_set_bit 339 arch/x86/kernel/cpu/hygon.c msr_set_bit(MSR_F10H_DECFG, msr_set_bit 436 arch/x86/kernel/cpu/intel.c if (msr_set_bit(MSR_IA32_MISC_ENABLE,