msm_writel        428 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	return msm_writel(value, ptr + (offset << 2));
msm_writel         89 drivers/gpu/drm/msm/adreno/a6xx_gmu.h 	return msm_writel(value, gmu->mmio + (offset << 2));
msm_writel        177 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	msm_writel((val), (ptr) + ((offset) << 2))
msm_writel         53 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h 	msm_writel(data, mdp4_kms->mmio + reg);
msm_writel        173 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	msm_writel(data, mdp5_kms->mmio + reg);
msm_writel         33 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	msm_writel(data, mdp5_mdss->mmio + reg);
msm_writel        192 drivers/gpu/drm/msm/dsi/dsi_host.c 	msm_writel(data, msm_host->ctrl_base + reg);
msm_writel         14 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h #define dsi_phy_write(offset, data) msm_writel((data), (offset))
msm_writel         44 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h 	msm_writel(data, reg);
msm_writel         19 drivers/gpu/drm/msm/edp/edp.h #define edp_write(offset, data) msm_writel((data), (offset))
msm_writel        119 drivers/gpu/drm/msm/hdmi/hdmi.h 	msm_writel(data, hdmi->mmio + reg);
msm_writel        170 drivers/gpu/drm/msm/hdmi/hdmi.h 	msm_writel(data, phy->mmio + reg);
msm_writel         89 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	msm_writel(data, pll->mmio_qserdes_com + offset);
msm_writel        100 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);
msm_writel        239 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	msm_writel(data, pll->mmio + reg);
msm_writel        410 drivers/gpu/drm/msm/msm_drv.h void msm_writel(u32 data, void __iomem *addr);
msm_writel        216 drivers/gpu/drm/msm/msm_gpu.h 	msm_writel(data, gpu->mmio + (reg << 2));
msm_writel        259 drivers/gpu/drm/msm/msm_gpu.h 	msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
msm_writel        260 drivers/gpu/drm/msm/msm_gpu.h 	msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));